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Initial commit.

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This commit is contained in:
Matt Harlum 2024-12-31 14:41:07 +13:00
commit b59fec459f
74 changed files with 166494 additions and 0 deletions
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.devcontainer/Dockerfile Normal file
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FROM stefanreinauer/amiga-gcc:latest
ARG DEBIAN_FRONTEND=noninteractive
RUN apt -y update && \
apt -y install sudo vim jq verilator
COPY ./verible.sh /verible.sh
RUN /verible.sh

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// For format details, see https://aka.ms/devcontainer.json. For config options, see the
// README at: https://github.com/devcontainers/templates/tree/main/src/debian
{
"name": "amiga-gcc-amitools",
// Or use a Dockerfile or Docker Compose file. More info: https://containers.dev/guide/dockerfile
"build": {
"dockerfile": "Dockerfile"
},
// Features to add to the dev container. More info: https://containers.dev/features.
// "features": {},
// Use 'forwardPorts' to make a list of ports inside the container available locally.
// "forwardPorts": [],
// "onCreateCommand": ".devcontainer/verible.sh",
// Configure tool-specific properties.
"customizations": {
"vscode": {
"extensions": [
"ms-vscode.cpptools",
"ms-vscode.cpptools-extension-pack",
"eamodio.gitlens",
"gigabates.m68k-lsp",
"mshr-h.veriloghdl"
]
}
},
// Uncomment to connect as root instead. More info: https://aka.ms/dev-containers-non-root.
"remoteUser": "ubuntu"
}

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#!/bin/bash -eu
case $(arch) in
aarch64):
ARCH=arm64
;;
x86_64):
ARCH=x86_64
;;
*)
echo "Unknown architecture"
exit 1
;;
esac
URL=$(curl -Ls https://api.github.com/repos/chipsalliance/verible/releases/latest | jq --raw-output ".assets[] | select(.name|test(\"${ARCH}\")).browser_download_url")
curl -Lsf ${URL} -o /tmp/verible.tar.gz
tar xf /tmp/verible.tar.gz -C /tmp
mv /tmp/verible-*/bin/* /usr/local/bin
rm -rf /tmp/verible*

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name: Generate release files
on:
push:
tags:
- "Release_**"
- "Rev**"
- "Proto**"
- "proto**"
workflow_dispatch:
jobs:
draft_release:
runs-on: ubuntu-latest
steps:
- name: Checkout
uses: actions/checkout@v3
- name: Zip Gerbers
run: zip -r Gerbers.zip Gerbers
- name: release
uses: softprops/action-gh-release@v1
with:
draft: true
files: |
Docs/Schematic.pdf
Docs/*.html
Gerbers/*.csv
Gerbers.zip
Binary/*.jed

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**/.DS_Store

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.vscode/c_cpp_properties.json vendored Normal file
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{
"configurations": [
{
"name": "Linux",
"includePath": [
"${workspaceFolder}/**",
"/opt/amiga/m68k-amigaos/ndk-include"
],
"defines": [
"CDBOOT=1"
],
"compilerPath": "/opt/amiga/bin/m68k-amigaos-gcc",
"cStandard": "gnu99",
"cppStandard": "gnu++14",
"intelliSenseMode": "linux-gcc-x64",
"configurationProvider": "ms-vscode.makefile-tools"
}
],
"version": 4
}

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{
"verilog.linting.linter": "verilator",
"verilog.formatting.verilogHDL.formatter": "verible-verilog-format",
"verilog.languageServer.veribleVerilogLs.enabled": true,
"verilog.languageServer.veribleVerilogLs.arguments": "--rules_config_search",
"[m68k]": {
"editor.rulers": []
}
}

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{
// See https://go.microsoft.com/fwlink/?LinkId=733558
// for the documentation about the tasks.json format
"version": "2.0.0",
"tasks": [
{
"label": "make",
"type": "shell",
"command": "cd rtl && make RIDE.jed",
"problemMatcher": [],
"group": {
"kind": "build",
"isDefault": true
}
},
{
"label": "flash",
"type": "shell",
"command": "cd rtl && make flash",
"problemMatcher": []
},
{
"label": "clean",
"type": "shell",
"command": "cd rtl && make clean",
"problemMatcher": []
}
]
}

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G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,8.0.5+1*
G04 #@! TF.CreationDate,2024-12-31T01:26:13+00:00*
G04 #@! TF.ProjectId,RIDE,52494445-2e6b-4696-9361-645f70636258,rev?*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 8.0.5+1) date 2024-12-31 01:26:13*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 #@! TA.AperFunction,Profile*
%ADD10C,0.100000*%
G04 #@! TD*
G04 APERTURE END LIST*
D10*
X0Y37084000D02*
X0Y0D01*
X82343605Y0D02*
X82089605Y0D01*
X0Y37211000D02*
X0Y37084000D01*
X82089605Y37211000D02*
X301605Y37211000D01*
X0Y37211000D02*
X301605Y37211000D01*
X82343605Y152400D02*
X82343605Y37084000D01*
X82343605Y152400D02*
X82343605Y0D01*
X82089605Y37211000D02*
X82343605Y37211000D01*
X82343605Y37211000D02*
X82343605Y37084000D01*
X301605Y0D02*
X82089605Y0D01*
X0Y0D02*
X301605Y0D01*
M02*

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M48
; DRILL file {KiCad 8.0.5+1} date 2024-12-31T01:26:13+0000
; FORMAT={-:-/ absolute / metric / decimal}
; #@! TF.CreationDate,2024-12-31T01:26:13+00:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,8.0.5+1
; #@! TF.FileFunction,NonPlated,1,4,NPTH
FMAT,2
METRIC
%
G90
G05
M30

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M48
; DRILL file {KiCad 8.0.5+1} date 2024-12-31T01:26:13+0000
; FORMAT={-:-/ absolute / metric / decimal}
; #@! TF.CreationDate,2024-12-31T01:26:13+00:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,8.0.5+1
; #@! TF.FileFunction,Plated,1,4,PTH
FMAT,2
METRIC
; #@! TA.AperFunction,Plated,PTH,ViaDrill
T1C0.254
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T2C1.000
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T3C1.440
%
G90
G05
T1
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X1.968Y36.195
X2.286Y21.92
X3.099Y18.237
X3.099Y12.319
X3.12Y23.498
X3.52Y11.263
X3.531Y10.49
X3.556Y16.535
X4.112Y17.209
X4.394Y12.789
X4.617Y8.123
X4.623Y16.535
X5.13Y17.186
X5.588Y21.539
X5.62Y18.081
X5.639Y5.817
X6.02Y13.249
X6.121Y8.103
X6.612Y8.688
X6.619Y18.652
X6.629Y13.729
X7.117Y8.128
X7.122Y18.075
X7.615Y13.619
X7.62Y18.669
X8.117Y8.672
X8.611Y8.103
X8.814Y5.817
X9.119Y8.661
X9.525Y21.082
X9.627Y8.103
X9.748Y28.438
X10.577Y20.068
X11.118Y11.252
X11.532Y8.839
X11.557Y9.906
X11.59Y18.28
X12.128Y9.347
X12.141Y8.369
X12.763Y34.239
X13.713Y31.379
X13.713Y28.204
X13.713Y34.786
X14.678Y34.125
X15.392Y21.692
X16.148Y21.698
X16.354Y7.884
X16.91Y21.749
X17.348Y13.183
X17.475Y5.548
X17.548Y14.589
X17.678Y21.743
X18.44Y36.119
X18.488Y13.954
X19.145Y20.301
X19.812Y6.426
X20.478Y33.172
X21.308Y15.317
X21.311Y6.452
X21.638Y28.004
X21.655Y35.386
X21.869Y14.681
X22.352Y15.317
X22.806Y20.939
X22.808Y6.528
X25.208Y6.563
X25.832Y20.879
X27.2Y13.395
X27.607Y20.965
X27.608Y5.878
X29.208Y6.588
X31.061Y20.939
X31.239Y13.395
X31.671Y5.75
X31.877Y21.107
X33.223Y20.637
X33.651Y34.979
X34.769Y15.097
X37.208Y5.75
X39.624Y20.637
X40.407Y5.718
X40.716Y20.637
X41.859Y6.655
X43.18Y35.636
X44.103Y35.636
X45.076Y7.781
X45.898Y18.974
X46.527Y19.969
X47.256Y6.413
X48.687Y17.453
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X49.292Y6.886
X49.297Y20.043
X49.5Y14.935
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X51.029Y18.44
X51.791Y17.983
X52.142Y7.089
X52.7Y19.129
X53.31Y13.439
X53.899Y3.16
X54.326Y8.918
X54.783Y7.547
X55.291Y19.993
X55.291Y6.988
X55.479Y35.494
X55.799Y8.918
X56.307Y8.359
X57.323Y19.993
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X58.014Y35.494
X58.288Y6.886
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X59.8Y17.3
X60.249Y27.289
X60.282Y16.421
X61.489Y16.977
X61.506Y28.042
X61.519Y16.002
X61.519Y3.554
X61.743Y9.071
X61.77Y12.954
X61.844Y7.445
X61.895Y10.442
X62.84Y27.838
X63.144Y21.158
X63.932Y21.158
X64.08Y13.447
X64.08Y15.504
X64.13Y16.437
X64.313Y19.533
X64.897Y13.97
X65.43Y27.305
X66.7Y5.446
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X67.688Y12.192
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X69.109Y8.646
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X70.227Y5.547
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X72.878Y12.148
X73.508Y6.731
X73.526Y15.396
X74.165Y11.107
X74.244Y12.676
X75.053Y16.063
X75.053Y14.437
X75.5Y4.85
X76.098Y12.751
X76.327Y22.733
X77.952Y16.841
X79.373Y22.989
T2
X8.616Y35.143
X8.616Y32.603
X8.616Y30.063
X11.156Y35.143
X11.156Y32.603
X11.156Y30.063
X28.496Y33.284
X28.496Y30.744
X31.036Y33.284
X31.036Y30.744
X33.576Y33.284
X33.576Y30.744
X36.116Y33.284
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X38.656Y33.284
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X41.196Y33.284
X41.196Y30.744
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X46.276Y33.284
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X56.436Y33.284
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X58.976Y33.284
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X61.516Y33.284
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X64.056Y33.284
X64.056Y30.744
X66.242Y20.117
X66.596Y33.284
X66.596Y30.744
X68.782Y20.117
X69.136Y33.284
X69.136Y30.744
X71.322Y20.117
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X73.862Y20.117
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X78.942Y20.117
X79.604Y16.485
X79.604Y13.945
X79.604Y11.405
X79.604Y8.865
X79.604Y6.325
T3
X1.848Y24.868
X1.848Y2.008
X4.388Y24.868
X4.388Y2.008
X6.928Y24.868
X6.928Y2.008
X9.468Y24.868
X9.468Y2.008
X12.008Y24.868
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X14.548Y24.868
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X17.088Y24.868
X17.088Y2.008
X19.628Y24.868
X19.628Y2.008
X22.168Y24.868
X22.168Y2.008
X24.708Y24.868
X24.708Y2.008
X27.248Y24.868
X27.248Y2.008
X29.788Y24.868
X29.788Y2.008
X32.328Y24.868
X32.328Y2.008
X34.868Y24.868
X34.868Y2.008
X37.408Y24.868
X37.408Y2.008
X39.948Y24.868
X39.948Y2.008
X42.488Y24.868
X42.488Y2.008
X45.028Y24.868
X45.028Y2.008
X47.568Y24.868
X47.568Y2.008
X50.108Y24.868
X50.108Y2.008
X52.648Y24.868
X52.648Y2.008
X55.188Y24.868
X55.188Y2.008
X57.728Y24.868
X57.728Y2.008
X60.268Y24.868
X60.268Y2.008
X62.808Y24.868
X62.808Y2.008
X65.348Y24.868
X65.348Y2.008
X67.888Y24.868
X67.888Y2.008
X70.428Y24.868
X70.428Y2.008
X72.968Y24.868
X72.968Y2.008
X75.508Y24.868
X75.508Y2.008
X78.048Y24.868
X78.048Y2.008
X80.588Y24.868
X80.588Y2.008
M30

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Gerbers/RIDE_bom_jlc.csv Normal file
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"Qty","Comment","Designator","Footprint","LCSC Part #"
"21","0.1u","C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C12,C13,C16,C17,C18,C19,C20,C22,C23,C24","C_0603_1608Metric","C14663"
"2","10u","C14,C15","CP_EIA-3216-18_Kemet-A","C117023"
"2","10u","C21,C25","C_0805_2012Metric_Pad1.18x1.45mm_HandSolder","C15850"
"1","47uF","C26","CP_EIA-3216-18_Kemet-A_Pad1.58x1.35mm_HandSolder","C193224"
"1","LED","D1","LED_0603_1608Metric","C136120"
"1","Polyfuse 500mA Hold","F1","Fuse_1206_3216Metric_Pad1.42x1.75mm_HandSolder",""
"7","33","R6,R7,R9,R13,R14,R18,R19","R_0603_1608Metric","C23140"
"3","150","R12,R20,R21","R_0603_1608Metric","C22808"
"11","10k","R1,R2,R3,R4,R5,R8,R10,R11,R15,R16,R17","R_0603_1608Metric","C25804"
"3","74HCT245","U4,U8,U9","TSSOP-20_4.4x6.5mm_P0.65mm","C6779"
"2","74LVC245","U2,U3","TSSOP-20_4.4x6.5mm_P0.65mm","C7848"
"1","AZ1117-3.3","U7","SOT-89-3","C460428"
"1","SST39SF010","U1","TSOP-I-32_11.8x8mm_P0.5mm",""
"1","W9812G6KH-6","U5","TSOP-II-54_22.2x10.16mm_P0.8mm","C367430"
"1","XC95144XL-TQ100","U6","TQFP-100_14x14mm_P0.5mm","C45126"
"1","50MHz","X1","Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm","C46327"
1 Qty Comment Designator Footprint LCSC Part #
2 21 0.1u C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C12,C13,C16,C17,C18,C19,C20,C22,C23,C24 C_0603_1608Metric C14663
3 2 10u C14,C15 CP_EIA-3216-18_Kemet-A C117023
4 2 10u C21,C25 C_0805_2012Metric_Pad1.18x1.45mm_HandSolder C15850
5 1 47uF C26 CP_EIA-3216-18_Kemet-A_Pad1.58x1.35mm_HandSolder C193224
6 1 LED D1 LED_0603_1608Metric C136120
7 1 Polyfuse 500mA Hold F1 Fuse_1206_3216Metric_Pad1.42x1.75mm_HandSolder
8 7 33 R6,R7,R9,R13,R14,R18,R19 R_0603_1608Metric C23140
9 3 150 R12,R20,R21 R_0603_1608Metric C22808
10 11 10k R1,R2,R3,R4,R5,R8,R10,R11,R15,R16,R17 R_0603_1608Metric C25804
11 3 74HCT245 U4,U8,U9 TSSOP-20_4.4x6.5mm_P0.65mm C6779
12 2 74LVC245 U2,U3 TSSOP-20_4.4x6.5mm_P0.65mm C7848
13 1 AZ1117-3.3 U7 SOT-89-3 C460428
14 1 SST39SF010 U1 TSOP-I-32_11.8x8mm_P0.5mm
15 1 W9812G6KH-6 U5 TSOP-II-54_22.2x10.16mm_P0.8mm C367430
16 1 XC95144XL-TQ100 U6 TQFP-100_14x14mm_P0.5mm C45126
17 1 50MHz X1 Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm C46327

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Gerbers/RIDE_cpl_jlc.csv Normal file
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Designator,Val,Package,Mid X,Mid Y,Rotation,Layer
"C1","0.1u","C_0603_1608Metric",7.2390,5.8166,0.0000,bottom
"C2","0.1u","C_0603_1608Metric",10.3472,21.8389,180.0000,top
"C3","0.1u","C_0603_1608Metric",13.7128,33.0200,270.0000,top
"C4","0.1u","C_0603_1608Metric",13.7128,29.7180,90.0000,top
"C5","0.1u","C_0603_1608Metric",17.7292,4.2418,0.0000,top
"C6","0.1u","C_0603_1608Metric",19.0246,5.7340,0.0000,top
"C7","0.1u","C_0603_1608Metric",22.0980,5.7340,0.0000,top
"C8","0.1u","C_0603_1608Metric",24.3172,20.8991,0.0000,top
"C9","0.1u","C_0603_1608Metric",25.9700,5.7340,0.0000,top
"C10","0.1u","C_0603_1608Metric",29.3972,20.9245,0.0000,top
"C11","0.1u","C_0603_1608Metric",29.9968,5.7340,0.0000,top
"C12","0.1u","C_0603_1608Metric",38.8206,5.7340,180.0000,top
"C13","0.1u","C_0603_1608Metric",43.1800,7.7724,180.0000,bottom
"C14","10u","CP_EIA-3216-18_Kemet-A",65.4812,6.6802,90.0000,top
"C15","10u","CP_EIA-3216-18_Kemet-A",73.4822,6.6700,90.0000,top
"C16","0.1u","C_0603_1608Metric",75.0680,11.8821,90.0000,top
"C17","0.1u","C_0603_1608Metric",60.9960,11.2438,90.0000,bottom
"C18","0.1u","C_0603_1608Metric",60.9964,8.2590,90.0000,bottom
"C19","0.1u","C_0603_1608Metric",56.7926,7.4866,0.0000,bottom
"C20","0.1u","C_0603_1608Metric",56.0870,19.1794,0.0000,bottom
"C21","10u","C_0805_2012Metric_Pad1.18x1.45mm_HandSolder",55.2996,13.4473,0.0000,bottom
"C22","0.1u","C_0603_1608Metric",51.0870,19.1286,0.0000,bottom
"C23","0.1u","C_0603_1608Metric",50.6204,7.4612,0.0000,bottom
"C24","0.1u","C_0603_1608Metric",49.5028,16.5009,270.0000,bottom
"C25","10u","C_0805_2012Metric_Pad1.18x1.45mm_HandSolder",29.2080,13.3965,0.0000,bottom
"C26","47uF","CP_EIA-3216-18_Kemet-A_Pad1.58x1.35mm_HandSolder",46.8713,35.6108,180.0000,bottom
"D1","LED","LED_0603_1608Metric",2.7940,29.0830,0.0000,top
"F1","Polyfuse 500mA Hold","Fuse_1206_3216Metric_Pad1.42x1.75mm_HandSolder",52.7812,35.5346,180.0000,bottom
"R1","10k","R_0603_1608Metric",2.7940,35.1432,0.0000,top
"R2","10k","R_0603_1608Metric",2.7940,33.6550,0.0000,top
"R3","10k","R_0603_1608Metric",2.7940,32.1310,0.0000,top
"R4","10K","R_0603_1608Metric",20.0660,36.1188,180.0000,top
"R5","10K","R_0603_1608Metric",16.8910,36.1188,0.0000,top
"R6","33","R_0603_1608Metric",46.4312,5.6134,0.0000,top
"R7","33","R_0603_1608Metric",62.9412,4.0132,0.0000,top
"R8","10K","R_0603_1608Metric",65.5320,17.4498,180.0000,top
"R9","33","R_0603_1608Metric",65.7606,14.9352,270.0000,top
"R10","10K","R_0603_1608Metric",75.0680,16.0119,270.0000,top
"R11","10K","R_0603_1608Metric",76.9638,16.0119,270.0000,top
"R12","150","R_0603_1608Metric",76.9638,11.9150,270.0000,top
"R13","33","R_0603_1608Metric",74.2188,28.1128,270.0000,bottom
"R14","33","R_0603_1608Metric",72.7456,28.1128,270.0000,bottom
"R15","10K","R_0603_1608Metric",66.5864,28.1128,270.0000,bottom
"R16","10K","R_0603_1608Metric",64.0464,28.1128,270.0000,bottom
"R17","10K","R_0603_1608Metric",61.5064,28.1128,270.0000,bottom
"R18","33","R_0603_1608Metric",58.9664,28.1128,270.0000,bottom
"R19","33","R_0603_1608Metric",56.4264,28.1128,270.0000,bottom
"R20","150","R_0603_1608Metric",34.2900,4.7085,0.0000,top
"R21","150","R_0603_1608Metric",2.7940,30.6070,180.0000,top
"U1","SST39SF010","TSOP-I-32_11.8x8mm_P0.5mm",5.8668,13.3965,0.0000,top
"U2","74LVC245","TSSOP-20_4.4x6.5mm_P0.65mm",14.0426,17.2065,0.0000,top
"U3","74LVC245","TSSOP-20_4.4x6.5mm_P0.65mm",14.0426,9.3071,180.0000,top
"U4","74HCT245","TSSOP-20_4.4x6.5mm_P0.65mm",18.7928,31.8516,90.0000,top
"U5","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",29.2080,13.3965,0.0000,top
"U6","XC95144XL-TQ100","TQFP-100_14x14mm_P0.5mm",55.2996,13.4473,270.0000,top
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"X1","50MHz","Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm",42.8752,6.7310,270.0000,top
1 Designator Val Package Mid X Mid Y Rotation Layer
2 C1 0.1u C_0603_1608Metric 7.2390 5.8166 0.0000 bottom
3 C2 0.1u C_0603_1608Metric 10.3472 21.8389 180.0000 top
4 C3 0.1u C_0603_1608Metric 13.7128 33.0200 270.0000 top
5 C4 0.1u C_0603_1608Metric 13.7128 29.7180 90.0000 top
6 C5 0.1u C_0603_1608Metric 17.7292 4.2418 0.0000 top
7 C6 0.1u C_0603_1608Metric 19.0246 5.7340 0.0000 top
8 C7 0.1u C_0603_1608Metric 22.0980 5.7340 0.0000 top
9 C8 0.1u C_0603_1608Metric 24.3172 20.8991 0.0000 top
10 C9 0.1u C_0603_1608Metric 25.9700 5.7340 0.0000 top
11 C10 0.1u C_0603_1608Metric 29.3972 20.9245 0.0000 top
12 C11 0.1u C_0603_1608Metric 29.9968 5.7340 0.0000 top
13 C12 0.1u C_0603_1608Metric 38.8206 5.7340 180.0000 top
14 C13 0.1u C_0603_1608Metric 43.1800 7.7724 180.0000 bottom
15 C14 10u CP_EIA-3216-18_Kemet-A 65.4812 6.6802 90.0000 top
16 C15 10u CP_EIA-3216-18_Kemet-A 73.4822 6.6700 90.0000 top
17 C16 0.1u C_0603_1608Metric 75.0680 11.8821 90.0000 top
18 C17 0.1u C_0603_1608Metric 60.9960 11.2438 90.0000 bottom
19 C18 0.1u C_0603_1608Metric 60.9964 8.2590 90.0000 bottom
20 C19 0.1u C_0603_1608Metric 56.7926 7.4866 0.0000 bottom
21 C20 0.1u C_0603_1608Metric 56.0870 19.1794 0.0000 bottom
22 C21 10u C_0805_2012Metric_Pad1.18x1.45mm_HandSolder 55.2996 13.4473 0.0000 bottom
23 C22 0.1u C_0603_1608Metric 51.0870 19.1286 0.0000 bottom
24 C23 0.1u C_0603_1608Metric 50.6204 7.4612 0.0000 bottom
25 C24 0.1u C_0603_1608Metric 49.5028 16.5009 270.0000 bottom
26 C25 10u C_0805_2012Metric_Pad1.18x1.45mm_HandSolder 29.2080 13.3965 0.0000 bottom
27 C26 47uF CP_EIA-3216-18_Kemet-A_Pad1.58x1.35mm_HandSolder 46.8713 35.6108 180.0000 bottom
28 D1 LED LED_0603_1608Metric 2.7940 29.0830 0.0000 top
29 F1 Polyfuse 500mA Hold Fuse_1206_3216Metric_Pad1.42x1.75mm_HandSolder 52.7812 35.5346 180.0000 bottom
30 R1 10k R_0603_1608Metric 2.7940 35.1432 0.0000 top
31 R2 10k R_0603_1608Metric 2.7940 33.6550 0.0000 top
32 R3 10k R_0603_1608Metric 2.7940 32.1310 0.0000 top
33 R4 10K R_0603_1608Metric 20.0660 36.1188 180.0000 top
34 R5 10K R_0603_1608Metric 16.8910 36.1188 0.0000 top
35 R6 33 R_0603_1608Metric 46.4312 5.6134 0.0000 top
36 R7 33 R_0603_1608Metric 62.9412 4.0132 0.0000 top
37 R8 10K R_0603_1608Metric 65.5320 17.4498 180.0000 top
38 R9 33 R_0603_1608Metric 65.7606 14.9352 270.0000 top
39 R10 10K R_0603_1608Metric 75.0680 16.0119 270.0000 top
40 R11 10K R_0603_1608Metric 76.9638 16.0119 270.0000 top
41 R12 150 R_0603_1608Metric 76.9638 11.9150 270.0000 top
42 R13 33 R_0603_1608Metric 74.2188 28.1128 270.0000 bottom
43 R14 33 R_0603_1608Metric 72.7456 28.1128 270.0000 bottom
44 R15 10K R_0603_1608Metric 66.5864 28.1128 270.0000 bottom
45 R16 10K R_0603_1608Metric 64.0464 28.1128 270.0000 bottom
46 R17 10K R_0603_1608Metric 61.5064 28.1128 270.0000 bottom
47 R18 33 R_0603_1608Metric 58.9664 28.1128 270.0000 bottom
48 R19 33 R_0603_1608Metric 56.4264 28.1128 270.0000 bottom
49 R20 150 R_0603_1608Metric 34.2900 4.7085 0.0000 top
50 R21 150 R_0603_1608Metric 2.7940 30.6070 180.0000 top
51 U1 SST39SF010 TSOP-I-32_11.8x8mm_P0.5mm 5.8668 13.3965 0.0000 top
52 U2 74LVC245 TSSOP-20_4.4x6.5mm_P0.65mm 14.0426 17.2065 0.0000 top
53 U3 74LVC245 TSSOP-20_4.4x6.5mm_P0.65mm 14.0426 9.3071 180.0000 top
54 U4 74HCT245 TSSOP-20_4.4x6.5mm_P0.65mm 18.7928 31.8516 90.0000 top
55 U5 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 29.2080 13.3965 0.0000 top
56 U6 XC95144XL-TQ100 TQFP-100_14x14mm_P0.5mm 55.2996 13.4473 270.0000 top
57 U7 AZ1117-3.3 SOT-89-3 69.3530 6.8008 180.0000 top
58 U8 74HCT245 TSSOP-20_4.4x6.5mm_P0.65mm 70.6028 13.9622 180.0000 top
59 U9 74HCT245 TSSOP-20_4.4x6.5mm_P0.65mm 18.7928 31.8516 270.0000 bottom
60 X1 50MHz Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm 42.8752 6.7310 270.0000 top

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Kicad/.gitignore vendored Normal file
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**/.DS_Store
*.zip
*.xml
Gerbers
*-backups/*
*-bak
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kibot_errors.*
*.lck
fp-info-cache

14473
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3rdparty

662
Kicad/Libs/39SF010-TSOP.kicad_sym Normal file
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245
Kicad/Libs/MT48LC8M16A2P.kicad_sym Normal file
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36
Kicad/Makefile Normal file
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PROJECT=RIDE
KIBOT_CONF=./kibot/release.kibot.yaml
GERBER_OUTPUT=../Gerbers
DRILLS=$(GERBER_OUTPUT)/$(PROJECT)-NPTH.drl $(GERBER_OUTPUT)/$(PROJECT)-PTH.drl
GERBERS=$(GERBER_OUTPUT)/$(PROJECT)-B_Cu.gbl $(GERBER_OUTPUT)/$(PROJECT)-B_Mask.gbs $(GERBER_OUTPUT)/$(PROJECT)-B_Silkscreen.gbo $(GERBER_OUTPUT)/$(PROJECT)-Edge_Cuts.gm1 $(GERBER_OUTPUT)/$(PROJECT)-F_Cu.gtl $(GERBER_OUTPUT)/$(PROJECT)-F_Mask.gts $(GERBER_OUTPUT)/$(PROJECT)-F_Silkscreen.gto $(GERBER_OUTPUT)/$(PROJECT)-F_Paste.gtp $(GERBER_OUTPUT)/$(PROJECT)-B_Paste.gbp $(DRILLS)
JLCPCB=$(GERBER_OUTPUT)/$(PROJECT)_bom_jlc.csv $(GERBER_OUTPUT)/$(PROJECT)_cpl_jlc.csv
BOM=../Docs/$(PROJECT)_bom.html
.PHONY: release
all: $(GERBERS) $(JLCPCB) $(BOM) ../Docs/Schematic.pdf ../Docs/$(PROJECT)-ibom.html
schematic: ../Docs/Schematic.pdf
gerbers: $(GERBERS)
jlcpcb: $(JLCPCB)
bom: $(BOM)
ibom: ../Docs/$(PROJECT)-ibom.html
$(GERBERS) ../Docs/PCB.png: $(PROJECT).kicad_pcb
kibot -c $(KIBOT_CONF) Gerbers Drills Image
$(JLCPCB): $(PROJECT).kicad_pcb $(PROJECT).kicad_sch
kibot --skip-pre all -c $(KIBOT_CONF) JLCPCB_position JLCPCB_bom
../Docs/Schematic.pdf: $(PROJECT).kicad_sch
kibot -s all -c $(KIBOT_CONF) Schematic
../Docs/$(PROJECT)-ibom.html: $(PROJECT).kicad_pcb
kibot -s all -c $(KIBOT_CONF) IBOM
$(BOM): $(PROJECT).kicad_pcb $(PROJECT).kicad_sch
kibot --skip-pre all -c $(KIBOT_CONF) html_bom

7846
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83
Kicad/RIDE.kicad_dru Normal file
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# JLCPCB 4-Layer
(version 1)
(rule "Trace clearance (large)"
(constraint clearance (min 5mil))
(condition "A.Type == 'Track'"))
(rule "Via to track clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Net != B.Net && A.Type == 'Via"))
(rule "Drill hole-size"
(constraint hole_size (min 0.2mm) (max 6.3mm))
(condition "A.Type == 'hole'"))
(rule "Min. Via hole size"
(constraint hole_size (min 0.2mm))
(condition "A.Type == 'Via'"))
(rule "Min. Via Diameter"
(constraint via_diameter (min 0.45mm))
(condition "A.Type == 'Via'"))
(rule "PTH hole size"
(constraint hole_size (min 0.2mm) (max 6.35mm))
(condition "A.Pad_Type == 'Through-hole' && A.isPlated() && A.Type == 'Pad'"))
#(rule "Pad Size"
# (constraint length (min 1.0mm))
# (condition "A.Pad_Type == 'Through-hole' && A.isPlated() && A.Type == 'Pad'"))
#(rule "Minimum annular ring (PTH)"
# (constraint annular_width (min 0.3mm))
# (condition "A.Pad_Type == 'Through-hole' && A.Type == 'Pad'"))
(rule "Minimum annular ring"
(constraint annular_width (min 0.127mm))
(condition "A.Type != 'Pad'"))
(rule "Hole-to-hole clearance (different nets)"
(constraint hole_to_hole (min 0.50mm))
(condition "A.Net != B.Net"))
(rule "Via-to-Via clearance (same nets)"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type == 'Via' && B.type == 'Via' && A.Net == B.Net"))
#(rule "Pad-to-Pad clearance (Pad without hole, different nets)"
# (constraint clearance (min 0.127mm))
# (condition "A.Type == B.Type && A.Type == 'Pad' && A.Net != B.Net && A.Pad_Type == 'SMD' && B.Pad_Type == 'SMD"))
(rule "Pad-to-Pad clearance (Pad with hole, different nets)"
(constraint clearance (min 0.127mm))
(condition "A.isPlated() && B.isPlated() && A.Type == B.Type && A.Type == 'Pad' && A.Net != B.Net && A.Pad_Type == 'Through-hole' && B.Pad_Type == 'Through-hole"))
(rule "PTH to Track clearance"
(constraint hole_clearance (min 0.33mm))
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated() && B.Type == 'Track' && A.Net != B.Net"))
(rule "NPTH to Track clearance"
(constraint hole_clearance (min 0.2mm))
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && !A.isPlated() && B.Type == 'Track' && A.Net != B.Net"))
(rule "Pad to Track clearance"
(constraint clearance (min 3.5mil))
(condition "A.Type == 'Pad' && B.Type == 'Track' && A.Net != B.Net"))
(rule "Minimum width (external layers)"
(constraint track_width (min 0.09mm))
(condition "(A.existsOnLayer('F.Cu') || A.existsOnLayer('B.cu')) && A.Type == 'Track'"))
(rule "Minimum width (internal layers)"
(constraint track_width (min 0.127mm))
(condition "A.existsOnLayer('In*.Cu') && A.Type == 'Track'"))
(rule "Trace clearance (large)"
(constraint clearance (min 5mil))
(condition "A.Type == 'Track' && B.Type == 'Track' && A.Width != 4mil"))
(rule "Trace clearance (small)"
(constraint clearance (min 3.5mil))
(condition "A.Type == 'Track' && B.Type == 'Track' && A.Width == 4mil"))

43284
Kicad/RIDE.kicad_pcb Normal file
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83
Kicad/RIDE.kicad_prl Normal file
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@ -0,0 +1,83 @@
{
"board": {
"active_layer": 36,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 1,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 1.0
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36,
40
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"git": {
"repo_password": "",
"repo_type": "",
"repo_username": "",
"ssh_key": ""
},
"meta": {
"filename": "RIDE.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

678
Kicad/RIDE.kicad_pro Normal file
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@ -0,0 +1,678 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 1.1,
"height": 1.9812,
"width": 2.4892
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.254
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [
"silk_edge_clearance|100603686|102779372|4c8d48c5-0613-48ab-9e90-117de867139f|f88fccf5-dff4-46ba-9d6e-c597b5cf3178"
],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "ignore",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "ignore",
"lib_footprint_mismatch": "ignore",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.254,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.381,
"min_text_thickness": 0.12,
"min_through_hole_diameter": 0.254,
"min_track_width": 0.1016,
"min_via_annular_width": 0.05,
"min_via_diameter": 0.4,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.1016,
0.127,
0.1778,
0.2032,
0.254,
0.381
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.508,
"drill": 0.254
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
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],
[
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],
[
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],
[
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],
[
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],
[
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],
[
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],
[
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[
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],
[
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2,
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2,
2,
2,
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2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "ignore",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "warning",
"pin_to_pin": "error",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [
"4Mx16_DRAM"
],
"pinned_symbol_libs": []
},
"meta": {
"filename": "RIDE.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 6,
"clearance": 0.0889,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1016,
"via_diameter": 0.508,
"via_drill": 0.254,
"wire_width": 6
},
{
"bus_width": 6,
"clearance": 0.0889,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.381,
"via_diameter": 0.508,
"via_drill": 0.254,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"bom_export_filename": "",
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
},
{
"group_by": false,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Qty",
"name": "${QUANTITY}",
"show": true
},
{
"group_by": true,
"label": "DNP",
"name": "${DNP}",
"show": true
},
{
"group_by": false,
"label": "#",
"name": "${ITEM_NUMBER}",
"show": false
},
{
"group_by": false,
"label": "LCSC #",
"name": "LCSC #",
"show": false
},
{
"group_by": false,
"label": "Description",
"name": "Description",
"show": false
}
],
"filter_string": "",
"group_symbols": true,
"name": "",
"sort_asc": true,
"sort_field": "Reference"
},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.3,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"overbar_offset_ratio": 1.23,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "./",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"feab44e6-4b08-41e4-b530-15f510ae4435",
"Root"
],
[
"c0ff79ce-9ab4-478c-85b1-6ca23c34a022",
"RAM"
],
[
"620723ea-5538-4ecb-b94a-9d07a4a31841",
"IDE"
],
[
"bc37d56d-573a-4481-9877-e87b8667e33a",
"CPLD"
]
],
"text_variables": {}
}

1129
Kicad/RIDE.kicad_sch Normal file
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File diff suppressed because it is too large Load Diff

2
Kicad/fp-lib-table Normal file
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@ -0,0 +1,2 @@
(fp_lib_table
)

218
Kicad/kibot/release.kibot.yaml Normal file
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kibot:
version: 1
filters:
- name: 'exclude_kibuzzard'
type: 'generic'
comment: 'Exclude Kibuzzard stuff'
exclude_any:
- column: References
regex: '^kibuzzard.*'
- name: 'exclude_tht'
type: 'generic'
comment: 'Exclude thru-hole parts'
exclude_tht: true
- name: 'fix_rotation'
comment: 'Adjust rotation for JLC'
type: rot_footprint
rotations:
- ["^TSOP-II", 270.0]
- ["^TSOP-I-32", 270.0]
- ["^SOT-89", 180.0]
- ["^SW_DIP_SPSTx04", 270.0]
- ["^CP_EIA-3216-18_Kemet-A", 0.0]
- ["^SOT-363", 180.0]
variants:
- name: rotated
comment: 'Just a place holder for the rotation filter'
type: kibom
variant: rotated
pre_transform: 'fix_rotation'
preflight:
check_zone_fills: true
fill_zones: false
run_drc: true
run_erc: true
update_xml: true
ignore_unconnected: true
filters:
- error: 'pin_not_connected'
filter: 'Pin not connected'
- error: 'silk_overlap'
filter: 'Silkscreen overlap'
- error: 'pin_not_driven'
filter: 'Input pin not driven by output'
regex: 'Input pin not driven by any Output pins'
outputs:
- name: Gerbers
comment: "Generate gerber files"
type: gerber
dir: '../Gerbers'
options:
exclude_edge_layer: true
exclude_pads_from_silkscreen: true
plot_sheet_reference: false
plot_footprint_refs: true
plot_footprint_values: false
force_plot_invisible_refs_vals: false
tent_vias: true
use_protel_extensions: true
create_gerber_job_file: false
disable_aperture_macros: true
gerber_precision: 4.6
use_gerber_x2_attributes: false
use_gerber_net_attributes: false
line_width: 0.1
subtract_mask_from_silk: true
inner_extension_pattern: '.g%Nl'
use_aux_axis_as_origin: true
layers:
- F.Cu
- B.Cu
- In1.Cu
- In2.Cu
- F.SilkS
- B.SilkS
- F.Paste
- B.Paste
- F.Mask
- B.Mask
- Edge.Cuts
- name: Drills
comment: Drill files
type: excellon
dir: '../Gerbers'
options:
pth_id: '-PTH'
npth_id: '-NPTH'
metric_units: true
route_mode_for_oval_holes: false
pth_and_npth_single_file: false
use_aux_axis_as_origin: true
output: "%f%i.%x"
- name: Schematic
comment: "Output PDF Schematic"
type: pdf_sch_print
options:
frame: true
output: "../Docs/Schematic.pdf"
- name: IBOM
type: ibom
comment: "Generate HTML Interactive BOM"
dir: ../Docs
options:
include_tracks: true
layer_view: FB
highlight_pin1: true
include_nets: true
dark_mode: true
extra_fields: "LCSC #,Mouser #"
- name: 3dImage
type: render_3d
comment: "3D Render"
run_by_default: true
options:
ray_tracing: false
output: ../Docs/PCB.png
zoom: 8
view: top
no_tht: true
orthographic: true
download: false
width: 1300
height: 530
- name: Image
type: pcbdraw
comment: "Draw PCB"
options:
output: ../Docs/PCB.png
format: png
show_solderpaste: false
show_components: none
- name: 'JLCPCB_position'
comment: "Pick and place file, JLCPCB style"
type: position
options:
variant: rotated
output: '../Gerbers/%f_cpl_jlc.%x'
format: CSV
units: millimeters
separate_files_for_front_and_back: false
use_aux_axis_as_origin: true
only_smd: true
columns:
- id: Ref
name: Designator
- Val
- Package
- id: PosX
name: "Mid X"
- id: PosY
name: "Mid Y"
- id: Rot
name: Rotation
- id: Side
name: Layer
- name: 'JLCPCB_bom'
comment: "BoM for JLCPCB"
type: bom
options:
output: '../Gerbers/%f_%i_jlc.%x'
exclude_filter:
- 'exclude_tht'
- 'exclude_kibuzzard'
ref_separator: ','
columns:
- field: 'Quantity Per PCB'
name: Qty
- field: Value
name: Comment
- field: References
name: Designator
- Footprint
- field: 'LCSC #'
name: 'LCSC Part #'
csv:
hide_pcb_info: true
hide_stats_info: true
quote_all: true
- name: 'html_bom'
comment: "BoM"
type: bom
options:
output: '../Docs/%f_%i.%x'
exclude_filter:
- 'exclude_kibuzzard'
ref_separator: ','
columns:
- field: 'Quantity Per PCB'
name: Qty
- field: Value
name: Comment
- field: References
name: Designator
- Footprint
- field: 'Mouser #'
name: 'Mouser Part'
- field: 'LCSC #'
name: 'LCSC Part'
html:
title: '%f Bill of materials'
hide_pcb_info: true
hide_stats_info: true
quote_all: true
lcsc_link: "LCSC #"
mouser_link: "Mouser #"

5
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(sym_lib_table
(version 7)
(lib (name "MT48LC8M16A2P")(type "KiCad")(uri "${KIPRJMOD}/Libs/MT48LC8M16A2P.kicad_sym")(options "")(descr ""))
(lib (name "39SF010-TSOP")(type "KiCad")(uri "${KIPRJMOD}/Libs/39SF010-TSOP.kicad_sym")(options "")(descr ""))
)

80
README.md Normal file
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# 🏍 RIDE - A500+ Fast Ram + IDE
## IDE + 11.37 Megabyte Fast RAM for the A500/A1000/A2000/CDTV
![PCB](Docs/PCB3D.png?raw=True)
## Features
- Autoboot IDE, Kick 1.3 compatible Open Source driver [lide.device](https://github.com/LIV2/lide.device)
- 11.37MB Fast RAM - 1.5MB $C0/Ranger + 8MB Fast + 1.87 Bonus ($A00000)
## Table of contents
1. [Compatibility](#compatibility)
2. [Jumper settings](#jumper-settings)
3. [Connections](#connections)
4. [Programming](#programming)
5. [Ordering PCBs](#ordering-pcbs)
* [PCB Order details](#pcb-order-details)
* [PCB Assembly](#pcb-assembly)
* [Bill of Materials](#bill-of-materials)
6. [License](#license)
## Compatibility
Compatible with Kickstart 1.3 and up.
## Jumper settings
**IDE Off**: Close to disable IDE
**RAM1/RAM2**: Autoconfig RAM configuration
|RAM1|RAM2|Size|
|-|-|----|
|Open|Open|**8 MB**|
|Closed|Open|**4 MB**|
|Open|Closed|**2 MB**|
|Closed|Closed|**Disable**|
## Connections
* **LED**: Activity LED
* **OVR**: **(Optional)** if connected this will enable the Ranger ($C00000) and Bonus ($A00000) RAM regions.
Connect OVR to Gary pin 29 or pin 17 of the side expansion port
* **CFGIN/OUT**: These pins allow this device to co-exist with other Autoconfig devices.
If there are no other Autoconfig devices in your system you can just leave these unconnected.
If there *are* other Autoconfig devices you will want to use one of these to add the device to the chain.<br /><br />
In the Amiga 2000 you can connect CFGIN to U606 Pin 8 which will add the device to the end of the chain but **NOTE: This takes up the config signal for the leftmost slot (CN601) so do NOT install a Zorro card there**
## Programming
Program the CPLD using this [jed file](https://github.com/LIV2/RIDE/raw/master/Binary/RIDE.jed) - You can find instructions on how to do that [here](https://linuxjedi.co.uk/2020/12/01/programming-xilinx-jtag-from-a-raspberry-pi/)
IDE ROM can be programmed by booting from the latest lide-update.adf [here](https://github.com/LIV2/LIDE.device/releases/latest).
## Ordering PCBs
Download the latest Gerbers.zip from the latest release listed on the right-hand side of this page.
Also included in the release are the placement and bom files needed for JLCPCB's assembly service
### PCB Order details
This PCB has been designed to JLCPCB's 4-layer capabilities so I recommend ordering from them
* Layers: 4
* Surface finish: ENIG
* Remove Order Number: Yes
### PCB Assembly
The release files include the relevant BOM and CPL files for JLCPCB's Assembly service
You can use the following options:
* PCBA Type: Economic
* Assembly side: Top side
* Confirm Parts Placement: Yes (I recommend checking that all ICs have pin 1 in the correct location etc)
### Bill of materials
The Bill of materials can be found under [Releases](https://github.com/LIV2/RIDE/releases/latest)
## Acknowledgements
Thanks to [SukkoPera](https://github.com/SukkoPera) for supporting my early IDE prototype.
## License
[![License: GPL v2](https://img.shields.io/badge/License-GPL_v2-blue.svg)](https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html)
This project is licensed under the GPL-2.0 only license

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tmp/**
artifacts/**

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Software/Makefile Normal file
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SHELL:=/bin/bash
CURDIR:=$(shell dirname $(realpath $(firstword $(MAKEFILE_LIST))))
TMPDIR=$(CURDIR)/tmp/
ARTIFACTDIR:=$(CURDIR)/artifacts
.PHONY: all software clean
all: software
bootrom/bootrom:
$(MAKE) -C bootrom all
addram/addram:
$(MAKE) -C addram all
maprom/maprom:
$(MAKE) -C maprom all
software: bootrom/bootrom addram/addram maprom/maprom
clean:
$(MAKE) -C bootrom clean
$(MAKE) -C addram clean
$(MAKE) -C maprom clean
rm -rf $(ARTIFACTDIR)
rm -rf $(TMPDIR)
package: addram/addram bootrom/bootrom maprom/maprom
rm -rf $(TMPDIR)
mkdir -p $(TMPDIR)
mkdir -p $(ARTIFACTDIR)
cp $^ $(TMPDIR)
cd $(TMPDIR) && xdftool $(ARTIFACTDIR)/RIDE-Software.adf format RIDE $(addprefix + write ,$(notdir $^))
cd $(TMPDIR) && lha -c $(ARTIFACTDIR)/RIDE-Software.lha $(notdir $^)

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addram

18
Software/addram/.vscode/c_cpp_properties.json vendored Normal file
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@ -0,0 +1,18 @@
{
"configurations": [
{
"name": "Linux",
"includePath": [
"${workspaceFolder}/**",
"/opt/amiga/m68k-amigaos/ndk13-include"
],
"defines": [],
"compilerPath": "/opt/amiga/bin/m68k-amigaos-gcc",
"cStandard": "gnu17",
"cppStandard": "gnu++14",
"intelliSenseMode": "linux-gcc-x64",
"configurationProvider": "ms-vscode.makefile-tools"
}
],
"version": 4
}

6
Software/addram/.vscode/settings.json vendored Normal file
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@ -0,0 +1,6 @@
{
"files.associations": {
"exec.h": "c",
"stdint.h": "c"
}
}

16
Software/addram/Makefile Normal file
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PROJECT=addram
CC=m68k-amigaos-gcc
CFLAGS=-lamiga -mcrt=nix13 -mcpu=68000 -Wall
.PHONY: clean all
all: $(PROJECT)
OBJ = config.o \
addram.o
SRCS = $(OBJ:%.o=%.c)
addram: $(SRCS) *.h
${CC} -o $@ $(CFLAGS) $(SRCS)
clean:
-rm $(PROJECT)

286
Software/addram/addram.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/* This file is part of addram
* Copyright (C) 2023 Matthew Harlum <matt@harlum.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <exec/execbase.h>
#include <proto/exec.h>
#include <proto/expansion.h>
#include <string.h>
#include <stdio.h>
#include <stdbool.h>
#include <stdlib.h>
#include <proto/dos.h>
#include "addram.h"
#include "config.h"
#include "../include/board.h"
struct ExpansionBase *ExpansionBase = NULL;
struct ConfigDev *cd;
struct List *MemList;
struct MemHeader *Node, *Next;
char board[] = BOARDSTRING;
UBYTE *ConfigRegister = NULL;
int main (int argc, char *argv[])
{
struct ExecBase *SysBase = *((struct ExecBase **)4UL);
int rc = 0;
MemList = &SysBase->MemList;
struct Config *config = Configure(argc,argv);
if (config == NULL) {
usage();
}
if (config->dryRun) printf("Doing a dry-run.\n");
for (Node = (struct MemHeader *)MemList->lh_Head; (Next = (struct MemHeader *)Node->mh_Node.ln_Succ) != NULL; Node = Next) {
// It might seem like a mistake to check if mh_Upper is greater than BONUSRAM_START
// But this will allow it to find the block even if it was merged with the Fast RAM block
if ((int)Node->mh_Upper > BONUSRAM_START && (int)Node->mh_Upper <= BONUSRAM_END) {
printf("Error: Memory block already added\n");
rc = 5;
}
}
if (rc == 0 && (ExpansionBase = (struct ExpansionBase *)OpenLibrary((unsigned char *)"expansion.library",0)) != NULL) {
if ((cd = FindConfigDev(NULL,MANUF_ID,PROD_ID_IDE))) {
ConfigRegister = (UBYTE *)cd->cd_BoardAddr + 0x8000;
char * boardName = NULL;
if ((boardName = AllocMem(sizeof(board),MEMF_CLEAR)) != NULL) {
strcpy(boardName,board);
enableBonusRam();
ULONG bonusRamSize = sizeBonusRam(config);
if (bonusRamSize > 0x1FE000) {
printf("Error: Detected more ram than should be in Bonus region somehow...\n");
rc = 20;
} else if (bonusRamSize > 0) {
if (config->verbose) printf("Found Board at 0x%06lx! with BonusRam size of %ldkB\n",(long unsigned int)cd->cd_BoardAddr,(long int)(bonusRamSize >> 10));
if (!config->dryRun) {
if (addBonusRam(bonusRamSize,boardName,config) == false) {
return 5;
}
}
fixPriorities(boardName, config);
} else {
printf("Error: No memory found.\n");
rc = 10;
}
} else {
printf("Unable to allocate memory.\n");
rc = 5;
}
} else {
printf("Board not found.\n");
rc = 5;
}
} else {
printf("Couldn't open expansion.library\n");
rc = 20;
}
if (config) FreeMem(config,sizeof(struct Config));
if (ExpansionBase) CloseLibrary((struct Library *)ExpansionBase);
return rc;
}
/** fixPriorities
*
* Change the priority of the Ranger/Fast RAM block
* @param boardName Pointer to string containing the board name
* @param config Pointer to the config struct
*/
void fixPriorities(char *boardName, struct Config *config) {
struct MemHeader *FastNode = NULL;
struct MemHeader *RangerNode = NULL;
for (Node = (struct MemHeader *)MemList->lh_Head; (Next = (struct MemHeader *)Node->mh_Node.ln_Succ) != NULL; Node = Next) {
if ((int)Node == 0xC00000) {
RangerNode = Node;
} else if (Node == cd->cd_BoardAddr) {
FastNode = Node;
}
}
if (!config->dryRun) {
Forbid();
if (FastNode) {
FastNode->mh_Node.ln_Name = boardName;
if (config->fastPriority > 0) {
if (config->verbose) printf("Setting FastRAM priority to %d\n",config->fastPriority);
FastNode->mh_Node.ln_Pri = (BYTE)config->fastPriority;
// Re-enqueue the node because we changed the priority
Remove((struct Node *)FastNode);
Enqueue(MemList,(struct Node *)FastNode);
}
}
if (RangerNode) {
if (config->verbose) printf("Setting Ranger Priority to %d\n",(config->fastPriority-1));
RangerNode->mh_Node.ln_Pri = (BYTE)(config->fastPriority-1);
RangerNode->mh_Attributes &= ~(MEMF_24BITDMA | MEMF_KICK); // Make sure MEMF_24BITDMA and MEMF_KICK are not set for this block
// Re-enqueue the node because we changed the priority
Remove((struct Node *)RangerNode);
Enqueue(MemList,(struct Node *)RangerNode);
}
Permit();
}
}
/**
* SizeBonusRam
*
* Perform a simple memory test and return the size of Bonus RAM
*
* BonusRam uses address space $A00000-BEFFFF
* Normally Gary decodes these as CIA accesses on the 500(+)/600/1000/2000/CDTV etc
* It is therefore important to make sure our test won't trash the CIA if the access somehow hits a CIA
*
* @param config Pointer to the config struct
* @returns Size of Bonus RAM in bytes
*/
ULONG sizeBonusRam(struct Config *config) {
ULONG bonusRamSize = 0;
UWORD *testPtr = NULL;
UWORD saveWord;
if (config->verbose) {
printf("Testing address ");
}
for (ULONG i=BONUSRAM_START; i < BONUSRAM_END; i+=0x010000) {
// Restore Saved value from last iteration
if (testPtr != NULL) *testPtr = saveWord;
// Test memory at Offset+0xB00 as this will be harmless if we access a CIA
testPtr = (void *)(i+0xB00);
saveWord = *testPtr;
if (config->verbose) {
fprintf(stdout,"\b\b\b\b\b\b%06lx", (long unsigned int)i);
fflush(stdout);
}
*testPtr = (i>>8);
if (SysBase->SoftVer >= 36) {
CacheClearE(testPtr,2,CACRF_ClearI|CACRF_ClearD);
}
if (*testPtr != (i>>8)) {
break;
} else {
bonusRamSize += 0x010000;
}
}
// Restore Saved value
*testPtr = saveWord;
if (config->verbose) printf("\nDone.\n");
return bonusRamSize;
}
/**
* enableBonusRAM
*
* Poke the control register to enable Bonus RAM
*/
void enableBonusRam() {
*ConfigRegister |= BONUSRAM_EN;
}
/**
* disableBonusRAM
*
* Poke the control register to disable Bonus RAM
*/
void disableBonusRam() {
*ConfigRegister &= ~(BONUSRAM_EN);
}
/**
* addBonusRam
*
* Add Bonus RAM to the memory pool
* Optionally try to expand the Fast RAM pool to contain Bonus RAM too
* @param bonusRamSize Bonus RAM size in bytes
* @param boardName String pointer to board name string
* @param config Pointer to the config struct
* @returns success
*/
bool addBonusRam(ULONG bonusRamSize, char *boardName, struct Config *config) {
struct MemHeader *Node = NULL;
struct MemHeader *FastNode = NULL;
for (Node = (struct MemHeader *)MemList->lh_Head;
Node->mh_Node.ln_Succ != NULL;
Node = (struct MemHeader *)Node->mh_Node.ln_Succ) {
if (Node->mh_Upper == (void *)BONUSRAM_START) {
FastNode = Node;
break;
}
}
if (config->mergeFastAndBonus == true && FastNode != NULL) {
// Try to expand the Fast RAM pool to include the Bonus RAM
//
// Maybe not a smart idea to modify the memory & chunk lists like this - but this is why it's not the default option!
//
if (config->verbose) printf("Merging Fast ram & Bonus ram pools\n");
FastNode->mh_Upper = (void*)(BONUSRAM_START + bonusRamSize);
Deallocate(FastNode,(APTR)BONUSRAM_START,bonusRamSize);
return true;
}
for (Node = (struct MemHeader *)MemList->lh_Head; (Next = (struct MemHeader *)Node->mh_Node.ln_Succ) != NULL; Node = Next) {
// It might seem like a mistake to check if mh_Upper is greater than BONUSRAM_START
// But this will allow it to find the block even if it was merged with the Fast RAM block
if ((int)Node->mh_Upper > BONUSRAM_START && (int)Node->mh_Upper <= BONUSRAM_END) {
printf("Error: Memory block already added\n");
return false;
}
}
AddMemList(bonusRamSize,MEMF_FAST|MEMF_PUBLIC|MEMF_24BITDMA,(LONG)config->fastPriority-2,(APTR)BONUSRAM_START,(STRPTR)boardName);
return true;
}

31
Software/addram/addram.h Normal file
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#ifndef _ADDRAM_H
#define _ADDRAM_H
#include "exec/types.h"
#include "config.h"
// Compiler warning fixes
#ifndef CacheClearE
// Silence the "implicit declaration of function" warning for this...
void CacheClearE(APTR,ULONG,ULONG);
#endif
#undef FindConfigDev
// NDK 1.3 definition of FindConfigDev is incorrect which causes "makes pointer from integer without a cast" warning
struct ConfigDev* FindConfigDev(struct ConfigDev*, LONG, LONG);
// End fixes
#define BOARDSTRING "GottaGoFast!!!\0"
#define BONUSRAM_EN 0x20
#define BONUSRAM_START 0xA00000
#define BONUSRAM_END 0xBF0000
void enableBonusRam();
void disableBonusRam();
ULONG sizeBonusRam(Config *);
void fixPriorities(char *, Config *);
bool getArgs(int, char*[]);
bool addBonusRam(ULONG, char*, struct Config*);
#endif

85
Software/addram/config.c Normal file
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#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <proto/exec.h>
#include "config.h"
/**
* Configure
*
* Parse the command args and set the configuration appropriately
* @param argc
* @param argv
* @returns Pointer to a Config struct.
*/
struct Config* Configure(int argc, char *argv[]) {
struct Config *config = AllocMem(sizeof(struct Config),MEMF_ANY);
if (config == NULL) {
printf("Failed to allocate memory.\n");
return (NULL);
}
config->dryRun = false;
config->mergeFastAndBonus = false;
config->verbose = false;
config->fastPriority = 0;
bool success = true;
for (int i=1; i<argc; i++) {
if (argv[i][0] == '-') {
switch(argv[i][1]) {
case 'D':
case 'd':
config->dryRun = true;
break;
case 'v':
case 'V':
config->verbose = true;
break;
case 'p':
case 'P':
if (i+1 < argc && strlen(argv[i+1]) > 0) {
config->fastPriority = atoi(argv[i+1]);
printf("Setting priority to %d\n",config->fastPriority);
} else {
printf("Error: argument %s requires a priority.\n",argv[i]);
success = false;
}
break;
case 'm':
case 'M':
config->mergeFastAndBonus = true;
break;
default:
case '?':
case 'h':
case 'H':
usage();
success = false;
break;
}
}
}
if (success) {
return (config);
} else {
return (NULL);
}
}
/**
* usage
*
* Print the usage information
*/
void usage() {
printf("Usage: addram [-d] [-v] [-p <Priority>] [-f] [-h]\n\n");
printf(" -d - Dry run\n");
printf(" -v - Verbose\n");
printf(" -p - Priority\n");
printf(" -m - Try to merge Fast and BonusRam blocks \n");
printf(" -h - Help\n");
}

18
Software/addram/config.h Normal file
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#ifndef _CONFIG_H
#define _CONFIG_H
#include <stdbool.h>
#include <stdint.h>
typedef struct Config {
bool dryRun;
bool verbose;
bool mergeFastAndBonus;
int fastPriority;
} Config;
struct Config* Configure(int, char *[]);
void usage();
#endif

3
Software/bootrom/.gitignore vendored Normal file
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obj/**
*.rom
bootrom

27
Software/bootrom/Makefile Normal file
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PROGRAM=bootrom
INCLUDE=/opt/amiga/m68k-amigaos/ndk-include
AS=vasmm68k_mot
ASFLAGS=-Fhunk -I$(INCLUDE) -quiet -align
LINKER=vlink
LINKFLAGS=-bamigahunk -s -sc -sd -mrel
OBJDIR=obj
.PHONY: all clean rom
SRCS = $(PROGRAM).s
OBJS = $(SRCS:%.s=$(OBJDIR)/%.o)
all: $(PROGRAM)
rom: $(ROMNAME)
$(OBJDIR)/%.o: %.s
mkdir -p $(OBJDIR)
$(AS) $(ASFLAGS) -o $@ $<
$(PROGRAM): $(OBJS)
$(LINKER) $(LINKFLAGS) -o $@ $<
clean:
rm -f $(OBJDIR)/*.o
rm -f $(PROGRAM)

246
Software/bootrom/bootrom.s Normal file
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include exec/types.i
include exec/execbase.i
include exec/alerts.i
include exec/nodes.i
include exec/resident.i
include exec/memory.i
include exec/lists.i
include lvo/exec_lib.i
include lvo/expansion_lib.i
include libraries/configvars.i
include hardware/cia.i
include ../include/board.i
BonusEna = $3000
BonusBase = $A00000
BonusPri = 0
SysBase = 4
CIAA = $BFE001
; Frame Pointer offsets
ExpansionBase = -4
FastRamBase = -8
ControlBase = -12
;
Start: bra Init
rts
RomTag:
dc.w RTC_MATCHWORD
dc.l RomTag
dc.l EndCode
dc.b (RTF_COLDSTART)
dc.b 1
dc.b NT_LIBRARY
dc.b 0
dc.l Name
dc.l ID
dc.l Init
; A2 = ExpansionBase, A6 = SysBase
Init:
movem.l D2-D3/A2-A3/A6,-(SP)
link.w A5,#-16
move.l #0,FastRamBase(A5)
move.l #0,ExpansionBase(A5)
movea.l SysBase,A6
btst.b #CIAB_GAMEPORT0,CIAA ; Exit if LMB pressed
beq exit
moveq.l #0,D0
lea ExpansionName(PC),A1
jsr _LVOOpenLibrary(A6)
move.l D0,ExpansionBase(A5)
tst.l D0
beq exit
FindRam:
move.l D0,A6
;Check if board present
move.l #0,A0
.loop: move.l #MANUF_ID,D0
move.l #PROD_ID_RAM,D1
jsr _LVOFindConfigDev(A6)
tst.l D0
beq exit
move.l D0,A0
btst #CDB_SHUTUP,cd_Flags(A0)
bne .loop
move.l cd_BoardAddr(A0),A0
move.l A0,FastRamBase(A5)
FindCtrl:
;Check if board present
move.l #0,A0
move.l #MANUF_ID,D0
move.l #PROD_ID_IDE,D1
jsr _LVOFindConfigDev(A6)
tst.l D0
beq exit
move.l D0,A0
move.l cd_BoardAddr(A0),A0
add.l #$8000,A0
move.l A0,ControlBase(A5)
;; Sanity check, check to make sure that the memory block does not already exist
Sanity: move.l SysBase,A6
lea MemList(A6),A2
move.l LH_HEAD(A2),A2
.loop: move.l MH_UPPER(A2),D0
cmp.l #BonusBase,D0 ; Is this blocks Upper limit lower than BonusBase?
ble .next ; If yes ignore it
cmp.l #(BonusBase+$1F0000),D0 ; Is it's upper-bound higher than Bonus Base's upper bound?
bgt .next ; Yes, ignore it
.found: bra exit ; No, if we got here the BonusRAM block fits inside the current block so we must not add it again
.next: move.l LN_SUCC(A2),D0
tst.l D0 ; End of the list?
beq .notfound ; No matching block found, go ahead and add the Bonus RAM block
move.l D0,A2
bra.s .loop
.notfound
;; Turn on BonusRAM region
Enable: move.l ControlBase(A5),A0
or.b #$20,(A0)
;; Get the Bonus RAM size with a simple address test
Size: moveq.l #31,D3 ; Loop 31 times - A00000-BEFFFF
move.l #BonusBase+$B00,A2 ; We poke at Addr+$B00 because this address will not trash CIA registers if our overlay is not active/working
moveq.l #0,D2 ; BonusRAM Size
bra.s .start
.loop: move.w D1,(A2) ; Restore saved value
add.l #$10000,A2 ; Increment test address by 64K
add.l #$10000,D2 ; Increase BonusRAM size by 64K
.start: move.w (A2),D1 ; Save value at address
move.l A2,D0
lsr.l #8,D0
move.w D0,(A2) ; Store upper address bits
nop
nop
cmp.w (A2),D0 ; Compare memory value
bne.s .done ; Value didn't match
dbra D3,.loop
.done: move.w D1,(A2) ; Restore last saved value
tst.l D2 ; Did we find any RAM?
beq exit
;; Attempt to merge Z2 Fast with BonusRAM
;; A2 = Pointer to board/mem header
;; A1 = Pointer to Chunk
;; D2 = BonusSize
Merge: move.l #0,D3
move.l FastRamBase(A5),A2
move.l MH_UPPER(A2),D0 ; Check if board neighbors BonusRAM
cmp.l #BonusBase,D0
bne.s .NewBrd ; Nope
movea.l SysBase,A6
jsr _LVOForbid(A6)
lea MH_FIRST(A2),A3
.walk: move.l MC_NEXT(A3),D0 ; Skip through mem chunks until we get to the end
beq.s .last
move.l MC_NEXT(A3),A3
bra.s .walk
.last: move.l MC_BYTES(A3),D1 ; Add Chunk size to chunk address, see if chunk is at the end
move.l A3,D0
add.l D0,D1
cmp.l #BonusBase,D1
bne.s .MakeNew
move.l MC_BYTES(A3),D1 ; Yes it is, increase the chunk size by BonusSize
add.l D2,D1
move.l D1,MC_BYTES(A3) ; And store it back
bra.s .FixMH
.MakeNew: move.l #BonusBase,D0 ; No free chunk at the end of Z2 Board, Add a new chunk
move.l D0,MC_NEXT(A3)
move.l #BonusBase,A3
move.l #0,MC_NEXT(A3)
move.l D2,MC_BYTES(A3)
;; Now fixup the MemHeader to reflect the new memory size
.FixMH: move.l #BonusBase,D0 ; Add BonusSize to BonusBase
add.l D2,D0
move.l D0,MH_UPPER(A2) ; Store it as the MemHeader Upper limit
move.l MH_FREE(A2),D0 ; Add BonusSize to MemFree
add.l D2,D0
move.l D0,MH_FREE(A2) ; Save back to MemFree
move.l FastRamBase(A5),A2
lea GottaGoFast(PC),A3
move.l A3,LN_NAME(A2)
jsr _LVOPermit(A6)
bra.s .done
;; Couldn't expand an existing block so we just create a whole new one
.NewBrd: move.l SysBase,A6
move.l D2,D0
move.l #MEMF_FAST|MEMF_PUBLIC|MEMF_24BITDMA,D1
move.l #BonusPri,D2
move.l #BonusBase,A0
lea GottaGoFast(PC),A1
jsr _LVOAddMemList(A6)
.done:
;; Kickstart versions below 2.0 give Slow RAM the same priority as Fast
;; So take the opportunity to change the priority to -5
FixPrio:
move.l SysBase,A6 ; Skip if running Kick 2 and up
cmp.l #36,SoftVer(A6)
bge.s .end
lea MemList(A6),A2
move.l LH_HEAD(A2),A3
.loop: cmp.l #$C00000,MH_LOWER(A3) ; Memory Node is Ranger?
blt .next
cmp.l #$DEFFFF,MH_UPPER(A3)
bgt .next
bra.s .found
.next move.l LN_SUCC(A3),D0 ; Keep looking
tst.l D0
beq.s .end
move.l D0,A3
bra.s .loop
.found move.b LN_PRI(A3),D0 ; If the priority is non-zero then don't change it
tst.b D0
bne.s .end
jsr _LVOForbid(A6)
move.l A3,A1 ; Remove and Re-enqueue and move it to the right position in the list
jsr _LVORemove(A6)
move.l A3,A1
move.l A2,A0
move.b #-5,LN_PRI(A3)
jsr _LVOEnqueue(A6)
jsr _LVOPermit(A6)
.end:
exit: move.l ExpansionBase(A5),D0
tst.l D0
beq .noexp
move.l SysBase,A6
move.l D0,A1
jsr _LVOCloseLibrary(A6)
.noexp: unlk A5
movem.l (SP)+,D2-D3/A2-A3/A6
moveq.l #0,D0
rts
GottaGoFast: dc.b "GottaGoFast!",0,0
cnop 0,4
ExpansionName: dc.b "expansion.library",0
Name: dc.b "RIDE.library",0
ID: dc.b "RIDE Support",0
EndCode:

8
Software/include/board.h Normal file
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@ -0,0 +1,8 @@
#ifndef __BOARD_H
#define MANUF_ID 5194
#define PROD_ID_IDE 5
#define PROD_ID_RAM 4
#endif

3
Software/include/board.i Normal file
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@ -0,0 +1,3 @@
MANUF_ID = 5194
PROD_ID_RAM = 4
PROD_ID_IDE = 5

1
Software/maprom/.gitignore vendored Normal file
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@ -0,0 +1 @@
maprom

18
Software/maprom/.vscode/c_cpp_properties.json vendored Normal file
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@ -0,0 +1,18 @@
{
"configurations": [
{
"name": "Linux",
"includePath": [
"${workspaceFolder}/**",
"/opt/amiga/m68k-amigaos/ndk13-include"
],
"defines": [],
"compilerPath": "/opt/amiga/bin/m68k-amigaos-gcc",
"cStandard": "gnu17",
"cppStandard": "gnu++14",
"intelliSenseMode": "linux-gcc-x64",
"configurationProvider": "ms-vscode.makefile-tools"
}
],
"version": 4
}

11
Software/maprom/Makefile Normal file
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@ -0,0 +1,11 @@
PROJECT=maprom
CC=m68k-amigaos-gcc
CFLAGS=-lamiga -mcrt=nix13 -mcpu=68000
.PHONY: clean all
all: $(PROJECT)
$(PROJECT): $(PROJECT).c
$(CC) $(CFLAGS) $^ -o $@
clean:
-rm $(PROJECT)

208
Software/maprom/maprom.c Normal file
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@ -0,0 +1,208 @@
// SPDX-License-Identifier: GPL-2.0-only
/* This file is part of maprom
* Copyright (C) 2023 Matthew Harlum <matt@harlum.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <exec/execbase.h>
#include <proto/exec.h>
#include <proto/expansion.h>
#include <string.h>
#include <stdio.h>
#include <stdbool.h>
#include <proto/dos.h>
#include <dos/dos.h>
#include "../include/board.h"
#define MAPROM_EN 1<<4
#define ROM_256K 0x040000
#define ROM_512K 0x080000
char *ks_filename;
char *ext_filename;
bool write_ext_rom;
bool disable_maprom;
struct Library *DosBase;
struct ExecBase *SysBase;
struct ExpansionBase *ExpansionBase = NULL;
void cleanup();
bool copyRom(char *, APTR, ULONG);
int getArgs(int, char* []);
ULONG getFileSize(char *);
int main(int argc, char *argv[])
{
SysBase = *((struct ExecBase **)4UL);
DosBase = OpenLibrary("dos.library",0);
if (DosBase == NULL) {
return 0;
}
printf("RIDE MapROM tool\n");
if (getArgs(argc,argv))
{
ULONG romSize = 0;
APTR destination = (void *)0xF80000;
if ((ExpansionBase = (struct ExpansionBase *)OpenLibrary("expansion.library",0)) != NULL) {
struct ConfigDev *cd = NULL;
if (cd = (struct ConfigDev*)FindConfigDev(NULL,MANUF_ID,PROD_ID_IDE)) {
UBYTE *control_register = cd->cd_BoardAddr + 0x8000;
if (disable_maprom == true) {
*control_register &= ~(MAPROM_EN);
printf("MapROM disabled.\n");
} else {
printf("Programming kick file %s\n",ks_filename);
if ((romSize = getFileSize(ks_filename)) == 0) {
goto fatal;
};
if (romSize == ROM_256K || romSize == ROM_512K) {
if (copyRom(ks_filename, destination, romSize) != true) {
printf("Failed to write kickstart rom.\n");
goto fatal;
}
*control_register |= MAPROM_EN;
} else {
printf("Bad rom size, 256K/512K ROM required.\n");
goto fatal;
}
if (write_ext_rom) {
destination = (void *)0xF00000;
printf("Programming extended rom %s\n",ext_filename);
if ((romSize = getFileSize(ext_filename)) == 0) {
goto fatal;
};
if (copyRom(ext_filename, destination, romSize) != true) {
printf("Failed to write extended rom.\n");
goto fatal;
};
}
}
} else {
printf("Couldn't find board with Manufacturer/Prod ID of %d:%d\n",MANUF_ID,PROD_ID_IDE);
goto fatal;
}
} else {
printf("Couldn't open Expansion.library.\n");
goto fatal;
}
} else {
goto fatal;
}
printf("Reboot for changes to take effect.\n");
cleanup();
return (0);
fatal:
cleanup();
return (5);
}
int getArgs(int argc, char *argv[]) {
disable_maprom = false;
for (int i=1; i<argc; i++) {
if (argv[i][0] == '-') {
switch(argv[i][1]) {
case 'D':
case 'd':
disable_maprom = true;
break;
case 'K':
case 'k':
if (i+1 < argc) {
ks_filename = argv[i+1];
i++;
}
break;
case 'E':
case 'e':
if (i+1 < argc) {
ext_filename = argv[i+1];
i++;
write_ext_rom = true;
}
break;
}
}
}
if (ks_filename != NULL || disable_maprom == true) {
return 1;
} else {
printf("Usage: %s -k <kickstart> [-e <extended rom>] [-d]\n",argv[0]);
return 0;
}
}
ULONG getFileSize(char *filename) {
BPTR fileLock;
ULONG fileSize = 0;
struct FileInfoBlock *FIB;
FIB = (struct FileInfoBlock *)AllocMem(sizeof(struct FileInfoBlock),MEMF_CLEAR);
if ((fileLock = Lock(filename,ACCESS_READ)) != 0) {
if (Examine(fileLock,FIB)) {
fileSize = FIB->fib_Size;
}
} else {
printf("Error opening %s\n",filename);
}
if (fileLock) UnLock(fileLock);
if (FIB) FreeMem(FIB,sizeof(struct FileInfoBlock));
return (fileSize);
}
bool copyRom(char *filename, APTR destination, ULONG romSize) {
BPTR fh = Open(filename,MODE_OLDFILE);
bool success = 0;
if (fh) {
APTR buffer = AllocMem(romSize, 0);
if (buffer) {
Read(fh,buffer,romSize);
printf("Copying... ");
CopyMem(buffer,destination,romSize);
// Double-up 256K Kickstart ROMs
if ((ULONG)destination == 0xF80000 && romSize == ROM_256K) {
destination += romSize;
CopyMem(buffer,destination,romSize);
}
printf("Done!\n");
FreeMem(buffer,romSize);
success = true;
} else {
printf("Unable to allocate memory.\n");
}
}
if (fh) Close(fh);
return (success);
}
void cleanup() {
if (ExpansionBase) CloseLibrary((struct Library *)ExpansionBase);
if (DosBase) CloseLibrary((struct Library *)DosBase);
}

7
rtl/.gitignore vendored Normal file
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_xmsgs
tmp/
*.log
*.err
*.jed
*.prj
local.mk

6
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-parameter-name-style
-explicit-parameter-storage-type
-macro-name-style
-module-filename
-case-missing-default
-line-length

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`timescale 1ns / 1ps
/*
* Copyright (C) 2023 Matthew Harlum <matt@harlum.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
module IDE(
input [23:12] addr,
input [3:0] din,
input rw,
input ds_n,
input as_n,
input clk,
input ide_access,
input ide_enable,
output reg ide_enabled,
input reset_n,
input [1:0] z2_state,
output reg [3:0] dout,
output idecs1_n,
output idecs2_n,
output reg ior_n,
output reg iow_n,
output [1:0] rom_bank,
output ide_romen,
output reg otherram_en,
output reg enable_maprom,
output idereg_access,
output reg dtack
);
`include "globalparams.vh"
reg [1:0] rom_bankSel;
assign rom_bank = (ide_enabled) ? rom_bankSel : {1'b0,addr[16]};
assign idecs1_n = !(ide_access && addr[13:12] == 2'b01 && addr[16:15] == 2'b00) || !ide_enabled;
assign idecs2_n = !(ide_access && addr[13:12] == 2'b10 && addr[16:15] == 2'b00) || !ide_enabled;
assign ide_romen = !(ide_access && (!ide_enabled || addr[16]));
assign idereg_access = ide_access && ide_enabled && addr[16:15] == 2'b01;
reg [2:0] ds_delay;
always @(posedge clk or posedge ds_n)
begin
if (ds_n) begin
ds_delay <= 'b0;
iow_n <= 1;
ior_n <= 1;
end else begin
if (ds_delay < 3'd7) begin
ds_delay <= ds_delay + 1;
end
// IOR assertion delayed by ~100ns after as_n to meet t1 address Setup time for IOR
if (rw && !as_n && ds_delay > 3'd4)
ior_n <= 0;
// IOW asserted in S4, deasserted ~120ns later so that t4 IOW data hold time is met
if (!rw && !as_n) begin
if (ds_delay < 3'd5) begin
iow_n <= 0;
end else begin
iow_n <= 1;
end
end
end
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ide_enabled <= 0;
rom_bankSel <= 0;
otherram_en <= 0;
dtack <= 0;
end else begin
if (ide_enable && !rw && ide_access) ide_enabled <= 1;
if (idereg_access && z2_state == Z2_DATA && !dtack) begin
dtack <= 1;
if (idereg_access) begin
if (rw) begin
dout[3:0] <= {rom_bankSel[1:0],otherram_en,enable_maprom};
end else begin
rom_bankSel <= din[3:2];
otherram_en <= din[1];
enable_maprom <= din[0];
end
end
end else begin
dtack <= 0;
end
end
end
endmodule

55
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PROJECT=RIDE
PART=XC95144XL-10-TQ100
WORKDIR=tmp
DEFINES=makedefines
CABLE=usb21
CPLDFITFLAGS=-loc on -slew slow -init low -terminate keeper -optimize density -keepio
.PHONY: all clean timing
all: $(PROJECT).jed timing
$(PROJECT).prj: *.v
-$(shell rm -f $@)
-$(foreach source,$^,$(shell echo verilog work $(source) >> $@))
$(WORKDIR)/$(PROJECT).ngc: *.v $(PROJECT).prj
-@mkdir $(WORKDIR)
@sed -r "s#^(-ofn).*#\1 ..\/$@#g;s#^(-ifn).*#\1 ../$(PROJECT).prj#g;s#^(-define).*#\1 {$(DEFINES)}#g" template.xst > $@.xst
cd $(WORKDIR) && xst -ifn ../$@.xst -ofn $(PROJECT)-xst.log
$(WORKDIR)/%.ngd: $(WORKDIR)/%.ngc $(PROJECT).ucf
cd $(WORKDIR) && ngdbuild -p $(PART) -uc ../$(PROJECT).ucf ../$< ../$@
$(WORKDIR)/%.rpt $(WORKDIR)/%.vm6: $(WORKDIR)/%.ngd $(PROJECT).ucf
cd $(WORKDIR) && cpldfit $(CPLDFITFLAGS) -p $(PART) ../$< | egrep -v "^CS: block|^$$"
cp $(WORKDIR)/$(PROJECT).rpt .
%.jed: $(WORKDIR)/%.vm6
hprep6 -i $<
cp $@ ../Binary/
fit: $(WORKDIR)/$(PROJECT).vm6
%.tim: $(WORKDIR)/%.vm6
cd $(WORKDIR) && taengine -l ../$@ -f $(PROJECT)
timing: $(PROJECT).tim
clean:
-rm -rvf tmp
-rm *.jed
-rm *.prj
flash: $(PROJECT).jed
@echo "setMode -bs\n"\
"setCable -p $(CABLE)\n"\
"identify\n"\
"assignfile -p 1 -file $<\n"\
"erase -p 1\n"\
"program -p 1\n"\
"verify -p 1" | LD_PRELOAD=/opt/Xilinx/usb-driver/libusb-driver.so impact -batch

75
rtl/RIDE.ucf Normal file
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NET "DBUS<12>" LOC = "P96";
NET "DBUS<13>" LOC = "P97";
NET "DBUS<14>" LOC = "P99";
NET "DBUS<15>" LOC = "P1";
NET "ADDR<1>" LOC = "P56";
NET "ADDR<2>" LOC = "P60";
NET "ADDR<3>" LOC = "P58";
NET "ADDR<4>" LOC = "P59";
NET "ADDR<5>" LOC = "P73";
NET "ADDR<6>" LOC = "P74";
NET "ADDR<7>" LOC = "P76";
NET "ADDR<8>" LOC = "P77";
NET "ADDR<9>" LOC = "P78";
NET "ADDR<10>" LOC = "P79";
NET "ADDR<11>" LOC = "P80";
NET "ADDR<12>" LOC = "P81";
NET "ADDR<13>" LOC = "P82";
NET "ADDR<14>" LOC = "P85";
NET "ADDR<15>" LOC = "P86";
NET "ADDR<16>" LOC = "P87";
NET "ADDR<17>" LOC = "P89";
NET "ADDR<18>" LOC = "P90";
NET "ADDR<19>" LOC = "P91";
NET "ADDR<20>" LOC = "P92";
NET "ADDR<21>" LOC = "P93";
NET "ADDR<22>" LOC = "P94";
NET "ADDR<23>" LOC = "P95";
NET "BERR_n" LOC = "P42";
NET "UDS_n" LOC = "P29";
NET "LDS_n" LOC = "P30";
NET "RW" LOC = "P32";
NET "AS_n" LOC = "P28";
NET "RESET_n" LOC = "P35";
NET "ECLK" LOC = "P34";
NET "DTACK_n" LOC = "P52";
NET "OVR_n" LOC = "P71";
NET "CFGOUT_n" LOC = "P61";
NET "CFGIN_n" LOC = "P66";
NET "IDE_ENABLE" LOC = "P40";
NET "IOR_n" LOC = "P70";
NET "IOW_n" LOC = "P68";
NET "IDECS1_n" LOC = "P64";
NET "IDECS2_n" LOC = "P63";
NET "IDEBUF_OE" LOC = "P67";
NET "IDE_ROMEN" LOC = "P12";
NET "ROM_BANK<0>" LOC = "P49";
NET "ROM_BANK<1>" LOC = "P50";
NET "MEMCLK" LOC = "P27";
NET "RAM_SIZE<0>" LOC = "P36";
NET "RAM_SIZE<1>" LOC = "P39";
NET "MEMW_n" LOC = "P14";
NET "RAS_n" LOC = "P16";
NET "CAS_n" LOC = "P15";
NET "CKE" LOC = "P10";
NET "DQML" LOC = "P13";
NET "DQMH" LOC = "P11";
NET "RAMCS_n" LOC = "P17";
NET "RAMOE_n" LOC = "P37";
NET "BA<0>" LOC = "P18";
NET "BA<1>" LOC = "P19";
NET "MA<0>" LOC = "P22";
NET "MA<1>" LOC = "P23";
NET "MA<2>" LOC = "P24";
NET "MA<3>" LOC = "P25";
NET "MA<4>" LOC = "P2";
NET "MA<5>" LOC = "P3";
NET "MA<6>" LOC = "P4";
NET "MA<7>" LOC = "P6";
NET "MA<8>" LOC = "P7";
NET "MA<9>" LOC = "P8";
NET "MA<10>" LOC = "P20";
NET "MA<11>" LOC = "P9";

301
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`timescale 1ns / 1ps
/*
* Copyright (C) 2023 Matthew Harlum <matt@harlum.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
module SDRAM(
input [23:1] addr,
input [1:0] z2_state,
input uds_n,
input lds_n,
input ram_cycle,
input reset_n,
input rw,
input clk,
input eclk,
output reg [1:0] ba,
output reg [11:0] maddr,
output reg cas_n,
output reg ras_n,
output reg cs_n,
output reg we_n,
output reg cke,
output reg dqml,
output reg dqmh,
output reg dtack,
output reg init_done
);
`include "globalparams.vh"
`define cmd(ARG) \
{ras_n, cas_n, we_n} <= ARG;
localparam tRP = 1;
localparam tRCD = 1;
localparam tRFC = 3;
localparam CAS_LATENCY = 3'd2;
// RAS CAS WE
localparam cmd_nop = 3'b111,
cmd_active = 3'b011,
cmd_read = 3'b101,
cmd_write = 3'b100,
cmd_burst_terminate = 3'b110,
cmd_precharge = 3'b010,
cmd_auto_refresh = 3'b001,
cmd_load_mode_reg = 3'b000;
localparam mode_register = {
2'b0, // M10-11 - Reserved
1'b1, // M9 - No burst mode, Single access
2'b0, // M8-7 - Standard operation
CAS_LATENCY, // M6-4 - CAS Latency
1'b0, // M3 - Burst type
3'b0 // M2-0 - Burst length
};
reg [3:0] refresh_timer;
reg [1:0] refresh_request;
reg refreshing;
wire refreshreset = !refreshing & reset_n;
// Refresh roughly every 7.1uS / 8192 refreshes in 58ms
always @(posedge eclk or negedge refreshreset) begin
if (!refreshreset) begin
refresh_timer <= 4'h4;
end else begin
if (refresh_timer > 0) begin
refresh_timer <= refresh_timer - 1;
end
end
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
refresh_request <= 0;
end else begin
refresh_request <= {refresh_request[0], refresh_timer == 0};
end
end
localparam init_poweron = 4'b0000,
init_precharge = init_poweron + 1,
init_precharge_wait = init_precharge + 1,
init_load_mode = init_precharge_wait + 1,
start_refresh = init_load_mode + 1,
refresh_wait = start_refresh + 1,
idle = refresh_wait + 1,
active = idle + 1,
active_wait = active + 1,
data_read = active_wait + 1,
data_write = data_read + 1,
data_hold = data_write + 1,
precharge_wait = data_hold + 1;
(* fsm_encoding = "compact" *) reg [3:0] ram_state;
reg init_refreshed;
reg [1:0] timer_tRFC;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ram_state <= init_poweron;
init_refreshed <= 0;
init_done <= 0;
dtack <= 0;
cs_n <= 1;
cke <= 1;
dqmh <= 1;
dqml <= 1;
end else begin
case (ram_state)
// Showtime!
//
init_poweron:
begin
`cmd(cmd_nop)
cs_n <= 0;
ram_state <= init_precharge;
end
// Init precharge
//
init_precharge:
begin
`cmd(cmd_precharge)
maddr[10] <= 1'b1; // Precharge all banks
ram_state <= init_precharge_wait;
end
// Init precharge wait
//
// Wait for precharge to complete
init_precharge_wait:
begin
`cmd(cmd_nop)
ram_state <= start_refresh;
end
// Load mode register
//
init_load_mode:
begin
`cmd(cmd_load_mode_reg)
init_done <= 1;
maddr[11:0] <= mode_register;
ram_state <= precharge_wait;
end
// Refresh
//
// Start auto-refresh
start_refresh:
begin
`cmd(cmd_auto_refresh)
timer_tRFC <= 2'b11;
refreshing <= 1;
cs_n <= 0;
ram_state <= refresh_wait;
end
// Refresh wait
//
// Wait for refresh to finish
// During RAM initialization it will refresh twice then go to load the mode register
refresh_wait:
begin
`cmd(cmd_nop)
if (timer_tRFC > 0) begin
timer_tRFC <= timer_tRFC - 1;
ram_state <= refresh_wait;
end else begin
if (!init_done) begin
if (init_refreshed) begin
// If we just finished the second init refresh go load the mode register
ram_state <= init_load_mode;
end else begin
// Do a second init refresh
ram_state <= start_refresh;
init_refreshed <= 1;
end
end else begin
ram_state <= idle;
end
end
end
// Idle
//
// Refresh has priority over memory access
idle:
begin
`cmd(cmd_nop)
refreshing <= 0;
dqmh <= 1;
dqml <= 1;
cs_n <= 1;
if (refresh_request[1]) begin
ram_state <= start_refresh;
end else if (ram_cycle && (z2_state == Z2_START || z2_state == Z2_DATA)) begin
ram_state <= active;
end else begin
ram_state <= idle;
end
end
// Active
//
// Activate the row/bank
active:
begin
`cmd(cmd_active)
ram_state <= active_wait;
maddr[11:0] <= addr[21:10];
ba[1:0] <= addr[23:22];
cs_n <= 0;
end
// Wait
//
// Wait for tRCD and also wait until we see data strobes before committing writes
active_wait:
begin
`cmd(cmd_nop)
if (z2_state >= Z2_DATA) begin
dtack <= 1;
if (rw)
ram_state <= data_read;
else
ram_state <= data_write;
end else begin
ram_state <= active_wait;
end
end
// Read
//
data_read:
begin
`cmd(cmd_read)
maddr[11:0] <= {3'b010,addr[9:1]};
dqmh <= 0;
dqml <= 0;
ram_state <= data_hold;
end
// Write
//
// Commit the write then go back to idle state
data_write:
begin
`cmd(cmd_write)
maddr[11:0] <= {3'b010,addr[9:1]};
dqmh <= uds_n;
dqml <= lds_n;
ram_state <= precharge_wait;
end
// Hold
//
// On read cycles, take cke low until the end of the Zorro cycle in order to hold the output
data_hold:
begin
`cmd(cmd_nop)
if (z2_state != Z2_IDLE) begin
cke <= 0;
ram_state <= data_hold;
end else begin
cke <= 1;
ram_state <= precharge_wait;
end
end
// Wait for auto-precharge to complete
precharge_wait:
begin
`cmd(cmd_nop)
dtack <= 0;
ram_state <= idle;
end
endcase
end
end
endmodule

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/*
* Copyright (C) 2023 Matthew Harlum <matt@harlum.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
module Autoconfig (
input [23:1] addr,
input as_n,
input clk,
input rw,
input [3:0] din,
input reset_n,
input ovr_detect,
input bonus_en,
input ide_enabled,
input [1:0] ram_size,
input [1:0] z2_state,
input cfgin_n,
input enable_maprom,
output cfgout_n,
output ram_access,
output ide_access,
output autoconfig_cycle,
output reg [3:0] dout,
output reg dtack,
output reg ovl
);
`include "globalparams.vh"
// Autoconfig
localparam [15:0] mfg_id = 16'd5194;
localparam [31:0] serial = 32'd1;
reg ram_configured;
reg ide_configured;
reg [2:0] ide_base;
reg cdtv;
reg cdtv_configured;
reg cfgin;
reg cfgout;
reg maprom_enabled;
reg [2:0] zram_size;
reg [3:0] addr_match;
reg [1:0] ac_state;
localparam ac_ram = 2'b00,
ac_ide = 2'b01,
ac_done = 2'b10;
localparam SZ_0M = 2'b00,
SZ_2M = 2'b01,
SZ_4M = 2'b10,
SZ_8M = 2'b11;
wire [7:0] prodid [0:1];
assign prodid[ac_ram] = 8'd4;
assign prodid[ac_ide] = 8'h5;
wire [3:0] boardSize [0:1];
assign boardSize[ac_ram] = {1'b1,zram_size};
assign boardSize[ac_ide] = 4'b0010; // 128K
assign autoconfig_cycle = (addr[23:16] == 8'hE8) && cfgin && !cfgout;
assign cfgout_n = ~cfgout;
// CDTV DMAC is first in chain.
// So we wait until it's configured before we talk
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
cdtv <= 0;
cdtv_configured <= 0;
end else begin
if (addr[23:16] == 8'hE8 && addr[8:1] == 8'h24 && !as_n && !rw) begin
cdtv_configured <= 1'b1;
end
if (addr[23:16] == 8'hE1 && !as_n && rw) begin // Read from CDTV NVRAM (won't work if CDTV switched to A500 mode...)
cdtv <= 1;
end
end
end
// These need to be registered at the end of a bus cycle
always @(posedge as_n or negedge reset_n) begin
if (!reset_n) begin
cfgout <= 0;
cfgin <= 0;
end else begin
`ifdef CDTV
cfgin <= ~cfgin_n && cdtv_configured;
`else
cfgin <= ~cfgin_n && (!cdtv || cdtv_configured);
`endif
cfgout <= (ac_state == ac_done);
end
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
zram_size <= 3'b000;
end else begin
case (ram_size)
SZ_8M: zram_size <= 3'b000;
SZ_4M: zram_size <= 3'b111;
SZ_2M: zram_size <= 3'b110;
default: zram_size <= 3'b000;
endcase
end
end
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
dout <= 'b0;
ac_state <= (ram_size == SZ_0M) ? (ac_ram + 1) : ac_ram;
dtack <= 0;
ide_base <= 3'b0;
ide_configured <= 0;
ram_configured <= 0;
addr_match <= 4'd0;
end else if (z2_state == Z2_DATA && autoconfig_cycle && !dtack) begin
dtack <= 1;
if (rw) begin
case (addr[8:1])
8'h00:
begin
case (ac_state)
ac_ram: dout <= 4'b1110; // Memory / Link to free mem pool
ac_ide: dout <= {3'b110, ide_enabled}; // IO / Read from autoboot rom
endcase
end
8'h01: dout <= {boardSize[ac_state]}; // Size: <RAMSIZE>, 128K
8'h02: dout <= ~(prodid[ac_state][7:4]); // Product number
8'h03: dout <= ~(prodid[ac_state][3:0]); // Product number
8'h04: dout <= ~{ac_state == ac_ram ? 1'b1 : 1'b0, 3'b000}; // Bit 1: Add to Z2 RAM space if set
8'h05: dout <= ~4'b0000;
8'h08: dout <= ~mfg_id[15:12]; // Manufacturer ID
8'h09: dout <= ~mfg_id[11:8]; // Manufacturer ID
8'h0A: dout <= ~mfg_id[7:4]; // Manufacturer ID
8'h0B: dout <= ~mfg_id[3:0]; // Manufacturer ID
8'h0C: dout <= ~serial[31:28]; // Serial number
8'h0D: dout <= ~serial[27:24]; // Serial number
8'h0E: dout <= ~serial[23:20]; // Serial number
8'h0F: dout <= ~serial[19:16]; // Serial number
8'h10: dout <= ~serial[15:12]; // Serial number
8'h11: dout <= ~serial[11:8]; // Serial number
8'h12: dout <= ~serial[7:4]; // Serial number
8'h13: dout <= ~serial[3:0]; // Serial number
8'h14: dout <= ~4'h0; // ROM Offset high byte high nibble
8'h15: dout <= ~4'h0; // ROM Offset high byte low nibble
8'h16: dout <= ~4'h0; // ROM Offset low byte high nibble
8'h17: dout <= ~4'h8; // ROM Offset low byte low nibble
8'h20: dout <= 4'b0;
8'h21: dout <= 4'b0;
default: dout <= 4'hF;
endcase
end else begin
if (addr[8:1] == 8'h26) begin
// We've been told to shut up (not enough memory space)
ac_state <= ac_state + 1;
end else if (addr[8:1] == 8'h24) begin
if (ac_state == ac_ram) begin
ram_configured <= 1'b1;
case (ram_size)
SZ_8M: addr_match[3:0] <= 4'b1111;
SZ_4M:
begin
case (din)
4'h2: addr_match[1:0] <= 2'b11;
4'h4: addr_match[2:1] <= 2'b11;
4'h6: addr_match[3:2] <= 2'b11;
endcase
end
SZ_2M:
begin
case (din)
4'h2: addr_match[0] <= 1'b1;
4'h4: addr_match[1] <= 1'b1;
4'h6: addr_match[2] <= 1'b1;
4'h8: addr_match[3] <= 1'b1;
endcase
end
endcase
end
ac_state <= ac_state + 1;
end else if (addr[8:1] == 8'h25) begin
if (ac_state == ac_ide) begin
ide_configured <= 1'b1;
ide_base <= din[3:1];
end
end
end
end else begin
dtack <= 0;
end
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ovl <= 1;
maprom_enabled <= enable_maprom && ovr_detect;
end else begin
if (addr[23:16] == 8'hBF && !as_n && !rw)
ovl <= 0;
end
end
wire fastram_access = (addr[23:21] == 3'b001 && addr_match[0]) || // $200000-3FFFFF
(addr[23:21] == 3'b010 && addr_match[1]) || // $400000-5FFFFF
(addr[23:21] == 3'b011 && addr_match[2]) || // $600000-7FFFFF
(addr[23:21] == 3'b100 && addr_match[3]); // $800000-9FFFFF
assign ide_access = (addr[23:17] == {4'hE, ide_base} && ide_configured);
wire bonus_access = (addr[23:16] >= 8'hA0) && (addr[23:16] <= 8'hBD); // A00000-BDFFFF Bonus RAM
wire otherram_access = bonus_access && bonus_en && ovr_detect;
wire ranger_access = (addr[23:16] >= 8'hC0) && (addr[23:16] <= 8'hD7) && ovr_detect;
wire bootrom_access = (addr[23:19] == 5'b00000 && ovl && maprom_enabled && rw);
wire kickrom_access = (addr[23:20] == 4'b1111 && (maprom_enabled == rw));
assign ram_access = fastram_access && ram_configured ||
bootrom_access ||
kickrom_access ||
otherram_access ||
ranger_access;
endmodule

4
rtl/globalparams.vh Normal file
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@ -0,0 +1,4 @@
localparam Z2_IDLE = 2'd0,
Z2_START = 2'd1,
Z2_DATA = 2'd2,
Z2_END = 2'd3;

30
rtl/template.xst Normal file
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set -tmpdir "."
set -xsthdpdir "."
run
-ifn IFN
-ifmt mixed
-ofn OFN
-ofmt NGC
-p xc9500xl
-top RIDE
-opt_mode speed
-opt_level 2
-iuc NO
-keep_hierarchy Yes
-netlist_hierarchy As_Optimized
-rtlview No
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-mux_extract Yes
-resource_sharing YES
-iobuf YES
-pld_mp YES
-pld_xp YES
-pld_ce YES
-wysiwyg NO
-equivalent_register_removal YES
-define {}

229
rtl/top.v Normal file
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`timescale 1ns / 1ps
/*
* Copyright (C) 2023 Matthew Harlum <matt@harlum.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
module RIDE(
inout [15:12] DBUS,
input [23:1] ADDR,
input BERR_n,
input UDS_n,
input LDS_n,
input RW,
input AS_n,
input RESET_n,
input ECLK,
input CFGIN_n,
output DTACK_n,
inout OVR_n,
output CFGOUT_n,
// IDE stuff
input IDE_ENABLE,
output IOR_n,
output IOW_n,
output IDECS1_n,
output IDECS2_n,
output IDEBUF_OE,
output IDE_ROMEN,
output [1:0] ROM_BANK,
// SDRAM Stuff
input [1:0] RAM_SIZE,
input MEMCLK,
output MEMW_n,
output RAS_n,
output CAS_n,
output CKE,
output DQML,
output DQMH,
output RAMCS_n,
output [11:0] MA,
output [1:0] BA,
output RAMOE_n
);
`include "globalparams.vh"
wire autoconfig_cycle;
wire [3:0] autoconfig_dout;
wire ram_dtack;
wire autoconf_dtack;
wire idereg_dtack;
reg ovr_detect;
wire ram_access;
wire ide_access;
wire idereg_access;
wire otherram_en;
wire [3:0] ideregister_dout;
wire ide_enabled;
wire ovl;
wire enable_maprom;
wire ram_ready;
wire bonus_en;
reg [1:0] uds_n_sync;
reg [1:0] lds_n_sync;
reg [2:0] as_n_sync;
reg [1:0] rw_sync;
// Detect if OVR has been connected
// A weak pull-down resistor will pull this signal low if disconnected.
//
// IDE & 8M Fast RAM can operate without OVR
// But A0 & C0 RAM can't
always @(posedge RESET_n) begin
ovr_detect <= OVR_n;
end
always @(posedge MEMCLK or negedge RESET_n) begin
if (!RESET_n) begin
uds_n_sync <= 2'b11;
lds_n_sync <= 2'b11;
as_n_sync <= 3'b111;
rw_sync <= 2'b11;
end else begin
uds_n_sync[1:0] <= {uds_n_sync[0],UDS_n};
lds_n_sync[1:0] <= {lds_n_sync[0],LDS_n};
as_n_sync[2:0] <= {as_n_sync[1:0],AS_n};
rw_sync <= {rw_sync[0],RW};
end
end
reg [1:0] z2_state;
always @(posedge MEMCLK or negedge RESET_n) begin
if (!RESET_n) begin
z2_state <= Z2_IDLE;
end else begin
case (z2_state)
Z2_IDLE:
begin
if (~as_n_sync[1] && (ram_access || autoconfig_cycle || idereg_access)) begin
z2_state <= Z2_START;
end
end
Z2_START:
begin
if (!uds_n_sync[1] || !lds_n_sync[1]) begin
z2_state <= Z2_DATA;
end
end
Z2_DATA:
begin
if (ram_dtack || autoconf_dtack || idereg_dtack) begin
z2_state <= Z2_END;
end
end
Z2_END:
if (as_n_sync[1]) begin
z2_state <= Z2_IDLE;
end
endcase
end
end
Autoconfig AUTOCONFIG (
.addr (ADDR),
.as_n (as_n_sync[1]),
.rw (rw_sync[1]),
.clk (MEMCLK),
.din (DBUS[15:12]),
.reset_n (RESET_n),
.ram_access (ram_access),
.ram_size (RAM_SIZE),
.ovr_detect (ovr_detect),
.bonus_en (bonus_en),
.ide_enabled (IDE_ENABLE),
.autoconfig_cycle (autoconfig_cycle),
.dout (autoconfig_dout),
.z2_state (z2_state),
.dtack (autoconf_dtack),
.ide_access (ide_access),
.enable_maprom (enable_maprom),
.cfgin_n (CFGIN_n),
.cfgout_n (CFGOUT_n),
.ovl (ovl)
);
// Force address to F8xxxx if ovl active for early boot overlay
wire [4:0] ram_addr_hi = (ovl) ? {4'b1111, (ADDR[19] | !ADDR[23])} : ADDR[23:19];
SDRAM SDRAM (
.addr ({ram_addr_hi, ADDR[18:1]}),
.z2_state (z2_state),
.uds_n (uds_n_sync[1]),
.lds_n (lds_n_sync[1]),
.ram_cycle (ram_access),
.reset_n (RESET_n),
.rw (rw_sync[1]),
.clk (MEMCLK),
.cke (CKE),
.ba (BA),
.maddr (MA),
.cas_n (CAS_n),
.ras_n (RAS_n),
.cs_n (RAMCS_n),
.we_n (MEMW_n),
.dqml (DQML),
.dqmh (DQMH),
.dtack (ram_dtack),
.eclk (ECLK),
.init_done (ram_ready)
);
IDE IDE (
.addr (ADDR[23:12]),
.din (DBUS[15:12]),
.dout (ideregister_dout),
.z2_state (z2_state),
.rw (RW),
.ds_n (uds_n_sync[1]),
.as_n (as_n_sync[1]),
.clk (MEMCLK),
.idecs1_n (IDECS1_n),
.idecs2_n (IDECS2_n),
.ide_access (ide_access),
.ide_enable (IDE_ENABLE),
.ide_enabled (ide_enabled),
.reset_n (RESET_n),
.iow_n (IOW_n),
.ior_n (IOR_n),
.rom_bank (ROM_BANK),
.ide_romen (IDE_ROMEN),
.idereg_access (idereg_access),
.otherram_en (otherram_en),
.enable_maprom (enable_maprom),
.dtack (idereg_dtack)
);
assign bonus_en = otherram_en && ovr_detect;
wire buf_en = (!UDS_n || !LDS_n || !RW);
assign RAMOE_n = !(ram_access && RESET_n && buf_en);
assign IDEBUF_OE = !(ide_access && ide_enabled && ADDR[16:15] == 2'b00 && buf_en);
wire [3:0] dout = (autoconfig_cycle) ? autoconfig_dout : ideregister_dout;
assign DBUS[15:12] = ((autoconfig_cycle || idereg_access) && RW && !uds_n_sync[1] && RESET_n) ? dout : 4'bZ;
assign OVR_n = (ram_access && ovr_detect) ? 1'b0 : 1'bZ;
assign DTACK_n = (ram_ready && ram_access && !AS_n && ovr_detect) ? 1'b0 : 1'bZ;
endmodule