65 Commits

Author SHA1 Message Date
SukkoPera
664253ad75 Add missing footprint 2019-03-03 11:33:34 +01:00
SukkoPera
74cfa8f891 Ready for prototypes 2019-03-03 11:32:47 +01:00
SukkoPera
30ad40eb80 Add JTAG connector pinout 2019-03-03 01:34:28 +01:00
SukkoPera
ab3d25345b More and more and more and more and more refinements... 2019-03-03 01:25:33 +01:00
SukkoPera
ddf203ce1c Stitched perimeter and more refinements 2019-03-03 00:56:19 +01:00
SukkoPera
dc8568836f Refinements here and there 2019-03-02 16:47:27 +01:00
SukkoPera
c9f53a0d83 Routing complete
Ground stitching and some refinements TBD
2019-03-02 12:36:28 +01:00
SukkoPera
d1745fc761 Almost there... 2019-03-02 01:15:34 +01:00
Giorgioggì
e92d533717
Update README.md 2019-03-01 10:19:54 +01:00
Giorgioggì
6e7d86c0b5
Update README.md 2019-03-01 10:16:14 +01:00
Giorgioggì
938dd2a5b9
Update README.md 2019-03-01 10:14:36 +01:00
Giorgioggì
f581a5bd9e
Update README.md 2019-03-01 10:12:15 +01:00
SukkoPera
fb1739712a Completed routing of data bus from CPU to RAM 2019-03-01 01:03:40 +01:00
SukkoPera
d7899fc917 Initial commit, schematic should be OK, PCB routing started 2019-03-01 00:45:08 +01:00
SukkoPera
0c194f7f6b Add .gitignore 2019-03-01 00:43:38 +01:00