SukkoPera
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664253ad75
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Add missing footprint
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2019-03-03 11:33:34 +01:00 |
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SukkoPera
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74cfa8f891
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Ready for prototypes
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2019-03-03 11:32:47 +01:00 |
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SukkoPera
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30ad40eb80
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Add JTAG connector pinout
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2019-03-03 01:34:28 +01:00 |
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SukkoPera
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ab3d25345b
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More and more and more and more and more refinements...
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2019-03-03 01:25:33 +01:00 |
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SukkoPera
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ddf203ce1c
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Stitched perimeter and more refinements
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2019-03-03 00:56:19 +01:00 |
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SukkoPera
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dc8568836f
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Refinements here and there
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2019-03-02 16:47:27 +01:00 |
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SukkoPera
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c9f53a0d83
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Routing complete
Ground stitching and some refinements TBD
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2019-03-02 12:36:28 +01:00 |
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SukkoPera
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d1745fc761
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Almost there...
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2019-03-02 01:15:34 +01:00 |
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Giorgioggì
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e92d533717
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Update README.md
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2019-03-01 10:19:54 +01:00 |
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Giorgioggì
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6e7d86c0b5
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Update README.md
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2019-03-01 10:16:14 +01:00 |
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Giorgioggì
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938dd2a5b9
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Update README.md
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2019-03-01 10:14:36 +01:00 |
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Giorgioggì
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f581a5bd9e
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Update README.md
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2019-03-01 10:12:15 +01:00 |
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SukkoPera
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fb1739712a
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Completed routing of data bus from CPU to RAM
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2019-03-01 01:03:40 +01:00 |
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SukkoPera
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d7899fc917
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Initial commit, schematic should be OK, PCB routing started
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2019-03-01 00:45:08 +01:00 |
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SukkoPera
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0c194f7f6b
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Add .gitignore
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2019-03-01 00:43:38 +01:00 |
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