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Clarify reasoning for DTACK holdoff
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@ -259,14 +259,11 @@ assign LCASn = !(access_lcas | refresh_cas);
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assign OEn = !(!RWn | ((autoconfig_cycle | ram_cycle) & !ASn & DOE & BERRn) & RESETn);
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// DOE doesn't get asserted by Buster until the access cycle is in the correct phase with C1/Custom chips
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// For some reason this seems to sometimes assert late into S6 which doesn't give enough time to
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// propogate from the RAM through the buffers
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// So we need hold off DTACK using ASq (internally generated DOE) instead of ASn.
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// Gary's DTACK generation for Z2 RAM space doesn't enforce this phase relationship though!
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// This can result in DOE not being asserted until S6 which doesn't always give enough time for data to propogate through all the buffers.
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// We will enforce the correct phase ourselves by holding off DTACK until we're in the correct phase
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//
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// This is known to solve issues GadgetUK164 was experiencing with this card, and the odd crash I experienced.
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//
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// ASNq valid from middle of S3 which means no waitstates.
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// Using DOE instead of ASNq would cause a waitstate as DOE is not active until S4 rise
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reg C2;
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reg ASq;
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