mirror of
https://github.com/LIV2/GottaGoFaZt3r.git
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100 lines
3.0 KiB
Verilog
100 lines
3.0 KiB
Verilog
/*
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GottaGoFaZt3r
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Copyright 2022 Matthew Harlum
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GottaGoFaZt3r is licensed under a
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Creative Commons Attribution-ShareAlike 4.0 International License.
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You should have received a copy of the license along with this
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work. If not, see <http://creativecommons.org/licenses/by-sa/4.0/>.
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*/
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module Autoconfig (
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input autoconfig_cycle,
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input [6:0] ADDRL,
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input FCS_n,
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input CLK,
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input READ,
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input [3:0] DIN,
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input RESET_n,
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input [1:0] z3_state,
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output reg [3:0] ram_base_addr,
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output reg CFGOUT_n,
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output reg dtack,
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output reg configured,
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output reg shutup,
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output reg [3:0] DOUT
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);
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`include "globalparams.vh"
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`ifndef makedefines
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`define SERIAL 32'd421
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`define PRODID 8'h72
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`endif
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localparam [15:0] mfg_id = 16'h07DB;
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localparam [7:0] prod_id = `PRODID;
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localparam [31:0] serial = `SERIAL;
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// Register Config in/out at end of bus cycle
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always @(posedge FCS_n or negedge RESET_n)
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begin
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if (!RESET_n) begin
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CFGOUT_n <= 1'b1;
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end else begin
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CFGOUT_n <= !configured && !shutup;
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end
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end
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always @(posedge CLK or negedge RESET_n)
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begin
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if (!RESET_n) begin
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DOUT[3:0] <= 4'b0;
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configured <= 1'b0;
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dtack <= 1'b0;
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shutup <= 1'b0;
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ram_base_addr[3:0] <= 4'b0000;
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end else if (z3_state == Z3_DATA && autoconfig_cycle == 1) begin
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dtack <= 1;
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if (READ) begin
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case ({ADDRL[5:0],ADDRL[6]})
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7'h00: DOUT[3:0] <= 4'b1010; // Type: Zorro III Memory
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7'h01: DOUT[3:0] <= 4'b0100; // 256 MB
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7'h02: DOUT[3:0] <= ~prod_id[7:4]; // Product number
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7'h03: DOUT[3:0] <= ~prod_id[3:0]; // Product number
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7'h04: DOUT[3:0] <= ~4'b1011; // Memory device, Size Extension, Zorro III
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7'h05: DOUT[3:0] <= ~4'b0001; // Automatically sized by OS
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7'h08: DOUT[3:0] <= ~mfg_id[15:12]; // Manufacturer ID
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7'h09: DOUT[3:0] <= ~mfg_id[11:8]; // Manufacturer ID
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7'h0A: DOUT[3:0] <= ~mfg_id[7:4]; // Manufacturer ID
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7'h0B: DOUT[3:0] <= ~mfg_id[3:0]; // Manufacturer ID
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7'h0C: DOUT[3:0] <= ~serial[31:28]; // Serial number
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7'h0D: DOUT[3:0] <= ~serial[27:24]; // Serial number
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7'h0E: DOUT[3:0] <= ~serial[23:20]; // Serial number
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7'h0F: DOUT[3:0] <= ~serial[19:16]; // Serial number
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7'h10: DOUT[3:0] <= ~serial[15:12]; // Serial number
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7'h11: DOUT[3:0] <= ~serial[11:8]; // Serial number
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7'h12: DOUT[3:0] <= ~serial[7:4]; // Serial number
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7'h13: DOUT[3:0] <= ~serial[3:0]; // Serial number
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7'h20: DOUT[3:0] <= 4'b0;
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7'h21: DOUT[3:0] <= 4'b0;
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default: DOUT[3:0] <= 4'hF;
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endcase
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end else begin
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if (ADDRL[5:0] == 6'h13) begin
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// Shutup
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shutup <= 1;
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end else if (ADDRL[5:0] == 6'h11) begin
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// Write base address
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ram_base_addr <= DIN[3:0];
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configured <= 1;
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end
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end
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end else begin
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dtack <= 0;
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end
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end
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endmodule
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