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Previously ram_cycle would latch at FCSn asserted and not be cleared until another FCSn assertion happened This caused issues because FCS_n_sync would lead ram_cycle_sync by 1 clock and this caused false memory cycles to start because ram_cycle_sync would still be true when it shouldn't be.
4 lines
115 B
Systemverilog
4 lines
115 B
Systemverilog
localparam Z3_IDLE = 2'd0,
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Z3_START = 2'd1,
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Z3_DATA = 2'd2,
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Z3_END = 2'd3; |