mirror of
https://github.com/LIV2/GottaGoFaZt3r.git
synced 2025-12-06 00:32:44 +00:00
Matt Harlum
15ff8132f5
On reads, DTACK will now come out 3 clocks after the READ command to the RAM With a CAS latency of 2, the read data will be valid at READ+2 The A4091 latches data as soon as DTACK is seen, so this delay was needed to make sure the A4091 correctly latches data from GottaGoFaZt3r
58 lines
1.5 KiB
Makefile
58 lines
1.5 KiB
Makefile
PROJECT=GottaGoFaZt3r
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PART=XC95144XL-10-TQ100
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WORKDIR=tmp
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SERIAL=$(shell git rev-parse --short=8 HEAD)
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SERIAL=0
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DEFINES=makedefines autoconfig SERIAL=32'h${SERIAL}
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CABLE=usb21
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CPLDFITFLAGS=-loc on -slew slow -init low -terminate keeper -unused ground -power std -optimize speed -keepio
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.PHONY: all clean fit
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all: ../Binary/$(PROJECT).jed
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$(PROJECT).prj: *.v
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-$(shell rm -f $@)
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-$(foreach source,$^,$(shell echo verilog work $(source) >> $@))
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$(WORKDIR)/$(PROJECT).ngc: *.v $(PROJECT).prj
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-@mkdir $(WORKDIR)
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@sed -r "s#^(-ofn).*#\1 ..\/$@#g;s#^(-ifn).*#\1 ../$(PROJECT).prj#g;s#^(-define).*#\1 {$(DEFINES)}#g" template.xst > $@.xst
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cd $(WORKDIR) && xst -ifn ../$@.xst -ofn $(PROJECT)-xst.log
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$(WORKDIR)/%.ngd: $(WORKDIR)/%.ngc $(PROJECT).ucf
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cd $(WORKDIR) && ngdbuild -p $(PART) -uc ../$(PROJECT).ucf ../$< ../$@
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$(WORKDIR)/%.vm6: $(WORKDIR)/%.ngd $(PROJECT).ucf
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cd $(WORKDIR) && cpldfit $(CPLDFITFLAGS) -p $(PART) ../$< | egrep -v "^CS: block|^$$"
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%.jed: $(WORKDIR)/%.vm6
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hprep6 -i $<
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../Binary/%.jed: %.jed
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cp $< ../Binary/
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clean:
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-rm -rvf tmp
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-rm *.jed
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-rm *.prj
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fit: $(WORKDIR)/$(PROJECT).vm6
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$(WORKDIR)/%.tim: $(WORKDIR)/%.vm6
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cd $(WORKDIR) && taengine -l ../$@ -f $(PROJECT)
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timing: $(WORKDIR)/$(PROJECT).tim
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flash:
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@echo "setMode -bs\n"\
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"setCable -p $(CABLE)\n"\
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"identify\n"\
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"assignfile -p 1 -file ../Binary/$(PROJECT).jed\n"\
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"erase -p 1\n"\
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"program -p 1\n"\
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"verify -p 1\n"\
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"exit\n" > tmp/batch
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LD_PRELOAD=/opt/Xilinx/usb-driver/libusb-driver.so impact -batch tmp/batch
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