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Make state machine transitions explicit

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This commit is contained in:
Matt Harlum 2022-04-26 10:08:17 +00:00
parent 4419b895f3
commit 6ca15ca666
1 changed files with 25 additions and 14 deletions
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39
RTL/sdram.v
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@ -139,13 +139,13 @@ reg cycle_type = 0;
localparam ram_cycle_access = 1'b1;
localparam ram_cycle_refresh = 1'b0;
localparam access_cycle_start = 5'b00000,
access_cycle_wait = access_cycle_start+tRCD,
localparam ram_cycle_idle = 5'b00000,
access_cycle_wait = ram_cycle_idle+tRCD,
access_cycle_rw = access_cycle_wait+1,
access_cycle_hold = access_cycle_rw+1,
access_cycle_precharge = access_cycle_hold+2,
access_cycle_precharge = access_cycle_hold+1,
refresh_cycle_pre = 5'b00000,
refresh_cycle_auto = refresh_cycle_pre+tRP,
refresh_cycle_auto = refresh_cycle_pre+1,
refresh_cycle_end = refresh_cycle_auto+tRFC;
wire refreshreset = !refreshing & RESET_n;
@ -201,14 +201,14 @@ begin
`cmd(cmd_precharge)
maddr_r[10] <= 1'b1; // Precharge all banks
cycle_type <= ram_cycle_refresh;
ram_state[0] <= 1'b1;
ram_state <= refresh_cycle_auto;
cs_r_n[1:0] <= 2'b00; // Refresh all modules
refreshing <= 1'b1;
// If refresh_request not active and we're in a ram cycle, go do a ram access
end else if (ram_cycle_sync[1] && !FCS_n) begin
`cmd(cmd_active)
cycle_type <= ram_cycle_access;
ram_state[0] <= 1'b1;
ram_state <= access_cycle_wait;
maddr_r[12:0] <= ADDR[23:11];
ba_r[1:0] <= ADDR[25:24];
cs_r_n[1:0] <= {ADDR[26],~ADDR[26]};
@ -219,7 +219,6 @@ begin
end
end
end else begin
ram_state <= ram_state + 1;
if (cycle_type == ram_cycle_access) begin
case (ram_state)
@ -228,9 +227,10 @@ begin
// Wait for tRCD and also wait until we see data strobes before committing writes
access_cycle_wait: begin
`cmd(cmd_nop)
if (DS_n[3:0] == 4'b1111 && !RW || !DOE) begin // ! Is DOE needed here? no need to hold off on reads
ram_state <= access_cycle_wait;
end
if (DS_n[3:0] != 4'b1111 && DOE || RW)
ram_state <= access_cycle_rw;
else
ram_state <= access_cycle_wait; // No data strobes seen yet, hold off
end
// Read/Write
@ -249,6 +249,7 @@ begin
// Reads must return a full long regardless of DS (Zorro III Bus Specifications pg 3-3)
DQM_n[3:0] <= 4'b0000;
end
ram_state <= access_cycle_hold;
end
// Hold
@ -259,13 +260,18 @@ begin
dtack <= 0;
`cmd(cmd_nop)
if (!FCS_n && DS_n[3:0] != 4'b1111) begin
//if (RW)
if (RW)
CKE <= 0;
ram_state <= access_cycle_hold;
end else begin
CKE <= 1;
if (!FCS_n)
// If Data strobes went inactive before FCS_n then it must be a burst
// Go do the next burst cycle
ram_state <= access_cycle_wait;
else
// Otherwise precharge and return to idle state
ram_state <= access_cycle_precharge;
end
end
@ -273,19 +279,24 @@ begin
access_cycle_precharge: begin
`cmd(cmd_precharge)
maddr_r[10] <= 1'b1;
ram_state <= 0;
ram_state <= ram_cycle_idle;
end
default:
default: begin
// We should never get here...
`cmd(cmd_nop)
ram_state <= ram_state+1;
end
endcase
end else begin
ram_state <= ram_state + 1;
case (ram_state)
refresh_cycle_auto:
`cmd(cmd_auto_refresh)
refresh_cycle_end: begin
ram_state <= 0;
ram_state <= ram_cycle_idle;
end
default: