Matt Harlum
e8e521c2c9
Bootrom: Add a kickstart module to enable A0 Bonus RAM at boot
2023-02-20 10:07:43 +00:00
Matt Harlum
854bc89bf2
Addram: fix merge behaviour
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Previously cd_BoardAddr pointed to the FastRAM board but this was changed to be the Control register
This meant that it was looking for a memory region at the control register base
Instead just look through the MemList to find a bordering Fast RAM chunk
2023-02-20 09:52:04 +00:00
773287f07b
RTL: Latch ranger_enable on reset
2023-02-19 21:59:04 +00:00
d0897bac81
CFLASH: make sure to erase the right bank...
2023-02-19 21:50:21 +00:00
f60fe5d4c6
RTL: Latch maprom enable at reset, disable autoboot rom flag when IDE disabled
2023-02-19 21:07:07 +00:00
c79853e5d3
cflash: Slots
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Describe top/bottom half as slots rather than banks to make usage more obvious
2023-02-19 20:59:33 +00:00
d48bbc9217
RTL: Fixups
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* Expansion ignores rom vector if it is 0, set the offset to 8
* Fixup IDE ROM - needs to be available for full 64K range
* Change to BSC/AT-Bus Manuf/Prod id for IDE during testing
* Fixup autoconfig goofs
* IDE ROM goes away after first write to IDE space
2023-02-19 17:07:45 +00:00
ddb5ca0d42
cflash: fixup a bunch of mistakes & add IDE rom verify
2023-02-19 17:03:48 +00:00
e6b67651ef
PCB: Fix drill/component grid & U10 missing from bom
2023-02-09 15:57:40 +01:00
0e0f44079d
Add ground pours
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Apparently JLCPCB are now incapable of producing 4-layer PCBs with less than 30% copper on outer layers...
2023-02-08 19:06:37 +01:00
485bfdf4f3
Update PCB Render
2023-02-07 20:46:07 +01:00
7053c5d04a
PCB: Connect NC's of 39SF010 to GND
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This will allow people to substitute 39SF020/040 if the 010 ever becomes unobtanium
2023-02-07 13:34:51 +01:00
8b6bb936bc
RTL: Add Timespec for MEMCLK
2023-02-06 12:31:41 +00:00
c1c1da54fd
RTL: Fixup ctrl_access equation
2023-02-06 12:31:34 +00:00
27c7be8cc5
PCB: Connect another CPLD pin to OVR_n
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This should give more drive strength to make sure we can drive it low nice and fast
2023-02-06 00:37:01 +01:00
5c35ac866a
RTL: Add timing report
2023-02-05 23:49:21 +00:00
9744c8883c
RTL: Tweak OVR
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* Optimize OVR equations to make sure it is asserted as fast as possible, use less pterms
* Drive OVR with 2 pins to give stronger drive
2023-02-05 23:49:09 +00:00
e72216cccb
Software: check-in AddRam util
2023-02-04 20:04:11 +00:00
c997a51a82
CFLASH: couple of fixups
2023-02-04 20:01:56 +00:00
e49340b54a
PCB: Fixups
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* Tweak KEL connector hole sizes
* Fixup MT48LC8M16A2P - Had copied this from the 16M16 part and forgot to make A12 an NC
2023-02-03 22:31:45 +01:00
cf8e1047fd
PCB: Remove useless cfgin connection
2023-02-03 04:53:14 +00:00
6da20be77e
RTL: Fix autoconfig
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The CDTV's diag port connects config_in/out to gnd making them useless.
Wait until we see the DMAC get assigned it's address instead...
While we're at it make the ram disable switch work
2023-02-03 04:25:48 +00:00
4dadf7da12
CFLASH: Correct behavior for 1MB ROMs
2023-02-03 04:05:02 +00:00
4dd987e5e2
Check-in cflash util
2023-02-02 20:41:27 +00:00
9278b6d529
RTL: change product id
2023-02-02 16:34:37 +00:00
a78895edd2
PCB: Connect Flash A18 to CPLD
2023-01-31 21:56:53 +01:00
dd2af3eb49
RTL: Force flash to upper bank during early boot
2023-01-31 20:00:55 +00:00
2009964140
Add Github release workflow
2023-01-30 22:07:56 +01:00
a4445960d2
Add License
2023-01-30 22:00:06 +01:00
45121e7e62
PCB: Add 22 Ohm series resistors for SDRAM
2023-01-30 21:49:50 +01:00
32ce8518e5
PCB: Route Flash bank switch jumper
2023-01-30 20:58:57 +01:00
b4ba649a6c
PCB: More work...
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* Add DIP Switches for Ram/Rom/IDE config
* Route bank select signals for Flash rom
* Flip IDE to bottom of the board
* Add some bulk capacitors
2023-01-30 15:54:45 +01:00
5439eff66d
RTL: Pinswaps + Implement bank selection for Flash
2023-01-30 14:45:55 +00:00
9a2d326d15
RTL: Assign pins
2023-01-29 16:37:54 +00:00
705fdafaa7
PCB: More routing...
2023-01-29 15:37:33 +01:00
23a2416485
PCB: Keep on routing...
2023-01-28 22:18:10 +01:00
dc7cd4e1d2
PCB: Start routing PCB
2023-01-28 17:09:52 +01:00
7260dfed99
PCB: Change IDE address line connections to A9-11 (AT-Bus style)
2023-01-28 10:01:09 +01:00
fddb6dd55f
RTL: Fixup report generation
2023-01-23 06:32:10 +00:00
391f832be3
RTL: Continue implementation
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* Replace Gayle IDE Emulation with AT-Apollo style IDE
* Rework Autoconfig module to also config IDE & Control register devices
2023-01-23 06:29:18 +00:00
432480c480
PCB: Change IDE address line connections from A2-4 to A10-12 (Gayle vs AT-Apollo style IDE)
2023-01-22 21:16:29 +01:00
41581ce4e0
PCB: Add 39SF010 for IDE ROM
2023-01-22 16:48:56 +01:00
bcef15d6e2
Begin PCB design
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* Added footprint for KEL connector
* Added symbol for CDTV Diag port
* Initial schematic entry
2023-01-22 14:34:16 +01:00
1e90d4354e
Initial commit.
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Start with the HDL, need to replace gayle IDE with Apollo IDE
2023-01-21 13:54:22 +00:00
