mirror of
https://github.com/LIV2/CIDER.git
synced 2025-12-06 00:23:50 +00:00
RTL: FIX - Remove AS_n from OVR equation
Assert OVR as soon as we have an address match If OVR comes too late then Gary will miss it and BonusRam/Flash programming window will conflict with CIAs
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parent
772e5b44b1
commit
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2338
Binary/CIDER.jed
2338
Binary/CIDER.jed
File diff suppressed because it is too large
Load Diff
1081
RTL/CIDER.rpt
1081
RTL/CIDER.rpt
File diff suppressed because it is too large
Load Diff
@ -5,7 +5,7 @@ Design: CIDER
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Device: XC95144XL-10-TQ100
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Speed File: Version 3.0
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Program: Timing Report Generator: version P.20131013
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Date: Thu Aug 10 15:47:43 2023
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Date: Fri Aug 18 07:34:07 2023
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Timing Constraint Summary:
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@ -77,8 +77,8 @@ IDECS2_n 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5
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IDE_ROMEN 15.5 15.5 15.5 15.5 14.5 14.5 14.5 14.5
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IOR_n 15.5
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IOW_n 15.5
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OVR_1_n 20.1 20.1 20.1 20.1 20.1 20.1 20.1 18.7
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OVR_2_n 20.1 20.1 20.1 20.1 20.1 20.1 20.1 18.7
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OVR_1_n 20.1 20.1 20.1 20.1 20.1 20.1 20.1
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OVR_2_n 20.1 20.1 20.1 20.1 20.1 20.1 20.1
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RAMOE_n 15.5 15.5 15.5 15.9 15.9 15.9 15.9 15.9
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--------------------------------------------------------------------------------
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@ -141,7 +141,7 @@ DQML 10.3
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DTACK_n 31.3
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EXTEN_n 18.0
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FLASH_A18 18.0
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FLASH_A19 18.0
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FLASH_A19 19.0
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FLASH_CE_n 19.0
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IDEBUF_OE 19.4
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IDECS1_n 19.4
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@ -195,30 +195,30 @@ ADDR<11> 7.5
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ADDR<12> 7.5
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ADDR<13> 7.5
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ADDR<14> 7.5
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ADDR<15> 7.9
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ADDR<15> 7.5
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ADDR<16> 15.2
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ADDR<17> 15.2
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ADDR<18> 15.2
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ADDR<19> 15.2
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ADDR<1> 7.9
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ADDR<1> 7.5
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ADDR<20> 14.2
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ADDR<21> 14.2
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ADDR<22> 14.2
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ADDR<23> 14.2
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ADDR<2> 7.9
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ADDR<3> 7.9
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ADDR<4> 7.9
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ADDR<5> 7.9
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ADDR<6> 7.9
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ADDR<7> 7.9
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ADDR<8> 7.9
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ADDR<2> 7.5
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ADDR<3> 7.5
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ADDR<4> 7.5
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ADDR<5> 7.5
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ADDR<6> 7.5
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ADDR<7> 7.5
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ADDR<8> 7.5
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ADDR<9> 7.5
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AS_n 6.5
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DBUS<12> 8.3
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DBUS<13> 7.9
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DBUS<14> 8.3
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DBUS<15> 7.9
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FLASH_BANK_SEL_n 6.5
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FLASH_BANK_SEL_n 7.5
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FLASH_EN_n 6.5
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IDEEN_n 7.5
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LDS_n 6.5
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@ -226,7 +226,7 @@ RAM_EN_n 7.5
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RANGER_EN_n 6.5
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RESET_n 7.5
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RW 7.5
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UDS_n 7.5
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UDS_n 6.5
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--------------------------------------------------------------------------------
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Clock to Setup (tCYC) (nsec)
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@ -300,7 +300,7 @@ SDRAM/refresh_timer<3>.D 10.0 10.0 10.0 10.0
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AS_n_sync<1>.D 10.0
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AUTOCONFIG/ac_state<0>.D 11.0
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AUTOCONFIG/ac_state<1>.D 10.0 10.0
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AUTOCONFIG/ac_state<1>.D 11.0 11.0
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AUTOCONFIG/cdtv_configured.CE 10.0
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AUTOCONFIG/ctl_configured.CE 10.0 10.0
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AUTOCONFIG/ctrl_base<0>.CE 10.0 10.0
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@ -317,7 +317,7 @@ BA<1>.CE
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CAS_n.D
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CKE.CE
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CKE.D
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ControlReg/dtack.D 10.0 11.0 11.0 11.4
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ControlReg/dtack.D 11.0 11.4 11.8 11.8
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ControlReg/flash_progbank.D 11.0 11.0 11.0 11.0
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DQMH.D
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DQML.D
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@ -353,11 +353,11 @@ SDRAM/timer_tRFC<1>.D
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UDS_n_sync<1>.D
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autoconf_dtack.D
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autoconfig_dout<0>.CE
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autoconfig_dout<0>.D 11.4 11.4
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autoconfig_dout<0>.D 11.0 11.0
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autoconfig_dout<1>.CE
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autoconfig_dout<1>.D 11.0 11.0
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autoconfig_dout<2>.CE
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autoconfig_dout<2>.D 11.4 11.4
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autoconfig_dout<2>.D 11.0 11.0
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autoconfig_dout<3>.CE
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autoconfig_dout<3>.D 11.0 11.0
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ctrl_dout<1>.D 11.0 11.0 11.0 11.0
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@ -367,7 +367,7 @@ ds_delay_0_2.D
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dtack.D 10.0
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mapram_en.D 11.8 11.8 11.8 11.8
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ram_dtack.D
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z2_state_FSM_FFd1.D 11.0
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z2_state_FSM_FFd1.D 10.0
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z2_state_FSM_FFd2.D 11.4 17.7 18.7 18.7 18.7
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--------------------------------------------------------------------------------
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@ -424,7 +424,7 @@ BA<1>.CE
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CAS_n.D
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CKE.CE
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CKE.D
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ControlReg/dtack.D 11.4 11.4
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ControlReg/dtack.D 11.8 11.8
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ControlReg/flash_progbank.D 10.0 11.4 10.0
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DQMH.D
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DQML.D
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@ -581,7 +581,7 @@ ds_delay_0_2.D
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dtack.D
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mapram_en.D
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ram_dtack.D
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z2_state_FSM_FFd1.D 11.0
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z2_state_FSM_FFd1.D 10.0
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z2_state_FSM_FFd2.D
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--------------------------------------------------------------------------------
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@ -649,11 +649,11 @@ MA<10>.D
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MA<11>.D
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MA<1>.D 10.0
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MA<2>.D 11.0
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MA<3>.D 10.0
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MA<4>.D 11.0
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MA<3>.D 11.0
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MA<4>.D 10.0
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MA<5>.D 11.0
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MA<6>.D 10.0
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MA<7>.D 10.0
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MA<7>.D 11.0
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MA<8>.D 10.0
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MA<9>.D
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MEMW_n.D
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@ -728,7 +728,7 @@ z2_state_FSM_FFd2.D
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AS_n_sync<1>.D
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AUTOCONFIG/ac_state<0>.D 11.0
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AUTOCONFIG/ac_state<1>.D 10.0
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AUTOCONFIG/ac_state<1>.D 11.0
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AUTOCONFIG/cdtv_configured.CE 10.0
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AUTOCONFIG/ctl_configured.CE 10.0
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AUTOCONFIG/ctrl_base<0>.CE 10.0
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@ -758,7 +758,7 @@ MA<1>.D 11.0 11.0
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MA<2>.D 11.0 11.0
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MA<3>.D 11.0 11.0
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MA<4>.D 11.0 11.0
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MA<5>.D 11.4 11.4
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MA<5>.D 11.0 11.0
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MA<6>.D 11.0 11.0
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MA<7>.D 11.0 11.0
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MA<8>.D 11.0 11.0
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@ -776,7 +776,7 @@ SDRAM/ram_state_FSM_FFd3.D 11.4 10.0 10.0 11.4 11.4
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SDRAM/ram_state_FSM_FFd4.D 11.4 11.0 11.4 11.4
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SDRAM/refresh_request<1>.D
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SDRAM/refreshing.D 10.0 10.0
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SDRAM/timer_tRFC<0>.D 11.0 11.0
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SDRAM/timer_tRFC<0>.D 10.0 10.0
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SDRAM/timer_tRFC<1>.D 10.0 10.0
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UDS_n_sync<1>.D
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autoconf_dtack.D
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@ -863,11 +863,11 @@ MA<10>.D 11.0 11.0
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MA<11>.D 10.0 10.0
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MA<1>.D 11.0 10.0
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MA<2>.D 11.0 11.0
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MA<3>.D 11.0 10.0
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MA<4>.D 11.0 11.0
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MA<5>.D 11.4 11.0
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MA<3>.D 11.0 11.0
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MA<4>.D 11.0 10.0
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MA<5>.D 11.0 11.0
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MA<6>.D 11.0 10.0
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MA<7>.D 11.0 10.0
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MA<7>.D 11.0 11.0
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MA<8>.D 11.0 10.0
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MA<9>.D 10.0 10.0
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MEMW_n.D 10.0 10.0
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@ -881,9 +881,9 @@ SDRAM/ram_state_FSM_FFd1.D 10.0 11.4 11.4
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SDRAM/ram_state_FSM_FFd2.D 11.4 11.4 11.4 11.0 11.0
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SDRAM/ram_state_FSM_FFd3.D 11.4 11.4 11.4 10.0 10.0
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SDRAM/ram_state_FSM_FFd4.D 11.4 11.0 11.0 11.0 11.0
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SDRAM/refresh_request<1>.D 11.0
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SDRAM/refresh_request<1>.D 10.0
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SDRAM/refreshing.D 10.0 10.0 10.0
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SDRAM/timer_tRFC<0>.D 11.0 11.0 11.0 11.0
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SDRAM/timer_tRFC<0>.D 10.0 10.0 10.0 10.0
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SDRAM/timer_tRFC<1>.D 10.0 10.0 10.0 10.0
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UDS_n_sync<1>.D 10.0
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autoconf_dtack.D
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@ -942,7 +942,7 @@ z2_state_FSM_FFd2.D
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AS_n_sync<1>.D
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AUTOCONFIG/ac_state<0>.D 11.0
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AUTOCONFIG/ac_state<1>.D 10.0
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AUTOCONFIG/ac_state<1>.D 11.0
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AUTOCONFIG/cdtv_configured.CE
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AUTOCONFIG/ctl_configured.CE 10.0
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AUTOCONFIG/ctrl_base<0>.CE 10.0
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@ -995,11 +995,11 @@ SDRAM/timer_tRFC<1>.D
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UDS_n_sync<1>.D
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autoconf_dtack.D 10.0
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autoconfig_dout<0>.CE 10.0
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autoconfig_dout<0>.D 11.4
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autoconfig_dout<0>.D 11.0
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autoconfig_dout<1>.CE 10.0
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autoconfig_dout<1>.D 10.0
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autoconfig_dout<2>.CE 10.0
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autoconfig_dout<2>.D 11.4
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autoconfig_dout<2>.D 11.0
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autoconfig_dout<3>.CE 10.0
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autoconfig_dout<3>.D 11.0
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ctrl_dout<1>.D 10.0
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@ -1009,7 +1009,7 @@ ds_delay_0_2.D 10.0
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dtack.D
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mapram_en.D
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ram_dtack.D 11.0
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z2_state_FSM_FFd1.D 11.0
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z2_state_FSM_FFd1.D 10.0
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z2_state_FSM_FFd2.D 10.0 11.0
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--------------------------------------------------------------------------------
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@ -1049,7 +1049,7 @@ z2_state_FSM_FFd2.D 10.0 11.0
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AS_n_sync<1>.D
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AUTOCONFIG/ac_state<0>.D 11.0 11.0
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AUTOCONFIG/ac_state<1>.D 10.0 10.0
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AUTOCONFIG/ac_state<1>.D 11.0 11.0
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AUTOCONFIG/cdtv_configured.CE
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AUTOCONFIG/ctl_configured.CE 10.0 10.0
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AUTOCONFIG/ctrl_base<0>.CE 10.0 10.0
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@ -1066,7 +1066,7 @@ BA<1>.CE
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CAS_n.D
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CKE.CE
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CKE.D 10.0 10.0
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ControlReg/dtack.D 11.0 11.0
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ControlReg/dtack.D 11.4 11.4
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ControlReg/flash_progbank.D 11.4 11.4
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DQMH.D
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DQML.D
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@ -1116,7 +1116,7 @@ ds_delay_0_2.D 10.0 10.0
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dtack.D 10.0 10.0
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mapram_en.D 11.8 11.8 11.8
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ram_dtack.D 11.0 11.0 11.0 11.0
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z2_state_FSM_FFd1.D 11.0 11.0
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z2_state_FSM_FFd1.D 10.0 10.0
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z2_state_FSM_FFd2.D 11.4 10.0 11.0 11.4 10.0
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Path Type Definition:
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@ -264,7 +264,7 @@ assign RAMOE_n = !(ram_access && !AS_n && RESET_n);
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assign FLASH_CE_n = ~flash_access || AS_n;
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wire OVR = ((ram_access || ide_access || flash_access) && !AS_n) ? 1'b0 : 1'bZ;
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wire OVR = (ram_access || ide_access || flash_access) ? 1'b0 : 1'bZ;
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assign OVR_1_n = OVR;
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assign OVR_2_n = OVR;
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