mirror of
https://github.com/LIV2/CIDER.git
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Add EXTEN_n JP15 control signal
This commit is contained in:
parent
86ba867558
commit
5f992df8d8
1505
RTL/CIDER.rpt
1505
RTL/CIDER.rpt
File diff suppressed because it is too large
Load Diff
671
RTL/CIDER.tim
671
RTL/CIDER.tim
@ -5,7 +5,7 @@ Design: CIDER
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Device: XC95144XL-10-TQ100
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Speed File: Version 3.0
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Program: Timing Report Generator: version P.20131013
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Date: Sat Apr 22 13:28:38 2023
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Date: Sat Apr 22 13:51:46 2023
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Performance Summary:
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@ -73,7 +73,7 @@ IDECS2_n 15.5 15.5 15.5 15.5 15.5 14.5 14.5 14.5 14.5
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IDE_ROMEN 15.5 15.5 15.5 15.9 14.5 14.5 14.5 14.5
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OVR_1_n 19.7 20.1 20.1 20.1 20.1 20.1 20.1 20.1 11.0
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OVR_2_n 19.7 20.1 20.1 20.1 20.1 20.1 20.1 20.1 11.0
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RAMOE_n 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5
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RAMOE_n 15.5 15.5 15.9 15.9 15.9 15.9 15.9 15.9
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--------------------------------------------------------------------------------
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Pad to Pad (tPD) (nsec)
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@ -103,7 +103,7 @@ IDECS2_n
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IDE_ROMEN
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OVR_1_n
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OVR_2_n
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RAMOE_n 15.5
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RAMOE_n 15.9
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--------------------------------------------------------------------------------
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Clock Pad to Output Pad (tCO) (nsec)
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@ -131,6 +131,7 @@ DBUS<15> 30.1
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DQMH 10.3
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DQML 10.3
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DTACK_n 23.6
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EXTEN_n 10.3
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FLASH_A18 19.0
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FLASH_A19 18.0
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FLASH_CE_n 19.0
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@ -156,7 +157,7 @@ MEMW_n 10.3
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OVR_1_n 23.6
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OVR_2_n 23.6
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RAMCS_n 10.3
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RAMOE_n 19.0
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RAMOE_n 19.4
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RAS_n 10.3
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--------------------------------------------------------------------------------
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@ -182,7 +183,7 @@ ADDR<10> 6.5
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ADDR<11> 7.5
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ADDR<12> 7.5
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ADDR<13> 7.5
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ADDR<14> 7.5
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ADDR<14> 6.5
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ADDR<15> 7.5
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ADDR<16> 16.6
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ADDR<17> 16.6
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@ -202,18 +203,18 @@ ADDR<7> 7.9
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ADDR<8> 7.9
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ADDR<9> 7.5
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AS_n 6.5
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DBUS<12> 8.3
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DBUS<13> 8.7
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DBUS<14> 8.3
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DBUS<12> 7.9
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DBUS<13> 7.9
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DBUS<14> 7.9
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DBUS<15> 7.9
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FLASH_BANK_SEL 6.5
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FLASH_EN_n 6.5
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IDEEN_n 7.9
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IORDY 7.5
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LDS_n 6.5
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RAM_EN_n 6.5
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RAM_EN_n 7.5
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RANGER_EN_n 6.5
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RESET_n 6.5
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RESET_n 7.5
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RW 7.5
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UDS_n 6.5
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@ -288,9 +289,9 @@ SDRAM/refresh_timer<3>.D 10.0 10.0 10.0 10.0
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To \------------------------------------------------
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AS_n_sync<1>.D 10.0
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AS_n_sync<2>.D 11.0
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AUTOCONFIG/ac_state<0>.D 10.0
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AUTOCONFIG/ac_state<1>.D 10.0 10.0
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AS_n_sync<2>.D 10.0
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AUTOCONFIG/ac_state<0>.D 11.0
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AUTOCONFIG/ac_state<1>.D 11.0 11.0
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AUTOCONFIG/cdtv_configured.CE 10.0
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AUTOCONFIG/ctl_configured.CE 10.0 10.0
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AUTOCONFIG/ctrl_base<0>.CE 10.0 10.0
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@ -352,13 +353,13 @@ autoconfig_dout<0>.D 11.4 11.4
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autoconfig_dout<1>.CE
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autoconfig_dout<1>.D 11.4 11.4
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autoconfig_dout<2>.CE
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autoconfig_dout<2>.D 11.4 11.4
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autoconfig_dout<2>.D 11.0 11.0
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autoconfig_dout<3>.CE
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autoconfig_dout<3>.D 11.0 11.0
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ctrl_dout<1>.D 11.8 11.4 11.4
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ctrl_dout<1>.D 11.0 11.0 11.0
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dtack.D 11.0 11.4 11.4 11.4
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ide_dtack.D
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mapram_en.D 11.8 11.8 11.8
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mapram_en.D 11.4 11.4 11.4
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ram_dtack.D
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z2_state_FSM_FFd1.D 10.0
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z2_state_FSM_FFd2.D 11.0 20.1 20.1 20.1
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@ -419,7 +420,7 @@ BA<1>.CE
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CAS_n.D
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CKE.CE
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CKE.D
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ControlReg/dtack.D 11.0 11.4
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ControlReg/dtack.D 11.4 11.4
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ControlReg/flash_progbank.D 11.0 10.0
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DQMH.D
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DQML.D
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@ -466,10 +467,10 @@ autoconfig_dout<2>.CE
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autoconfig_dout<2>.D
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autoconfig_dout<3>.CE
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autoconfig_dout<3>.D
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ctrl_dout<1>.D 11.4 11.0
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dtack.D 11.4 11.4
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ide_dtack.D 11.4 11.4 11.8 11.8 10.0
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mapram_en.D 11.8 11.8
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ctrl_dout<1>.D 11.0 10.0
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dtack.D 11.4 11.8
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ide_dtack.D 11.0 11.0 11.0 11.4 10.0
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mapram_en.D 11.4 11.4
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ram_dtack.D
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z2_state_FSM_FFd1.D
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z2_state_FSM_FFd2.D 20.1 20.1 19.7 19.7 20.1 20.1 19.7 19.7
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@ -478,23 +479,23 @@ z2_state_FSM_FFd2.D 20.1 20.1 19.7 19.7 20.1 20.1 19.7 19.7
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Clock to Setup (tCYC) (nsec)
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(Clock: MEMCLK)
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\ From C C D D I I I I
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\ o o Q Q D D D D
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\ n n M M E E E E
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\ t t H L / / / /
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\ r r . . d d d i
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\ o o Q Q s s s d
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\ l l _ _ _ e
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\ R R d d d _
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\ e e e e e e
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\ g g l l l n
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\ / / a a a a
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\ d f y y y b
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\ t l < < < l
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\ a a 0 1 2 e
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\ c s > > > d
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\ k h . . . .
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\ . _ Q Q Q Q
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\ From C C D D E I I I
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\ o o Q Q X D D D
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\ n n M M T E E E
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\ t t H L E / / /
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\ r r . . N d d d
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\ o o Q Q _ s s s
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\ l l n _ _ _
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\ R R . d d d
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\ e e Q e e e
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\ g g l l l
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\ / / a a a
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\ d f y y y
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\ t l < < <
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\ a a 0 1 2
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\ c s > > >
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\ k h . . .
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\ . _ Q Q Q
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\ Q p
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\ r
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\ o
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@ -535,10 +536,10 @@ ControlReg/flash_progbank.D 11.4 10.0
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DQMH.D 11.0
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DQML.D 11.0
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IDE/ds_delay<0>.D
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IDE/ds_delay<1>.D 10.0
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IDE/ds_delay<2>.D 10.0
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IDE/ide_enabled.D 11.4
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IOW_n.D 10.0
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IDE/ds_delay<1>.D 10.0
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IDE/ds_delay<2>.D 10.0
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IDE/ide_enabled.D
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IOW_n.D 10.0
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LDS_n_sync<1>.D
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MA<0>.D
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MA<10>.D
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@ -577,35 +578,35 @@ autoconfig_dout<2>.CE
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autoconfig_dout<2>.D
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autoconfig_dout<3>.CE
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autoconfig_dout<3>.D
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ctrl_dout<1>.D 12.2
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dtack.D
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ctrl_dout<1>.D 11.4
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dtack.D 11.0
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ide_dtack.D
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mapram_en.D 11.8
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mapram_en.D 11.4
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ram_dtack.D
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z2_state_FSM_FFd1.D
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z2_state_FSM_FFd2.D
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z2_state_FSM_FFd2.D 20.1
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--------------------------------------------------------------------------------
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Clock to Setup (tCYC) (nsec)
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(Clock: MEMCLK)
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\ From L L M M M M M M
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\ D D A A A A A A
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\ S S < < < < < <
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\ _ _ 0 1 1 1 2 3
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\ n n > 0 1 > > >
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\ _ _ . > > . . .
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\ s s Q . . Q Q Q
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\ y y Q Q
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\ n n
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\ c c
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\ < <
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\ 0 1
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\ > >
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\ . .
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\ Q Q
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\
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\
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\ From I L L M M M M M
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\ D D D A A A A A
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\ E S S < < < < <
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\ / _ _ 0 1 1 1 2
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\ i n n > 0 1 > >
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\ d _ _ . > > . .
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\ e s s Q . . Q Q
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\ _ y y Q Q
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\ e n n
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\ n c c
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\ a < <
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\ b 0 1
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\ l > >
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\ e . .
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\ d Q Q
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\ .
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\ Q
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\
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\
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\
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@ -644,19 +645,19 @@ CKE.D
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ControlReg/dtack.D
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ControlReg/flash_progbank.D
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DQMH.D
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DQML.D 10.0
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IDE/ds_delay<0>.D 10.0
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DQML.D 11.0
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IDE/ds_delay<0>.D 10.0
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IDE/ds_delay<1>.D
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IDE/ds_delay<2>.D
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IDE/ide_enabled.D
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IDE/ide_enabled.D 11.4
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IOW_n.D
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LDS_n_sync<1>.D 11.0
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MA<0>.D 10.0
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MA<10>.D 10.0
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MA<11>.D 10.0
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MA<1>.D 10.0
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MA<2>.D 11.0
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MA<3>.D 11.0
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LDS_n_sync<1>.D 10.0
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MA<0>.D 10.0
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MA<10>.D 11.0
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MA<11>.D 10.0
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MA<1>.D 11.0
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MA<2>.D 11.0
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MA<3>.D
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MA<4>.D
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MA<5>.D
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MA<6>.D
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@ -693,22 +694,22 @@ dtack.D
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ide_dtack.D
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mapram_en.D
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ram_dtack.D
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z2_state_FSM_FFd1.D 10.0
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z2_state_FSM_FFd1.D 10.0
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z2_state_FSM_FFd2.D
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--------------------------------------------------------------------------------
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Clock to Setup (tCYC) (nsec)
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(Clock: MEMCLK)
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\ From M M M M M M O R
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\ A A A A A A V A
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\ < < < < < < L M
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\ 4 5 6 7 8 9 . C
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\ > > > > > > Q S
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\ . . . . . . _
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\ Q Q Q Q Q Q n
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\ .
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\ Q
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\ From M M M M M M M O
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\ A A A A A A A V
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\ < < < < < < < L
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\ 3 4 5 6 7 8 9 .
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\ > > > > > > > Q
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\ . . . . . . .
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\ Q Q Q Q Q Q Q
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\
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\
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\
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\
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\
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@ -767,16 +768,16 @@ MA<10>.D
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MA<11>.D
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MA<1>.D
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MA<2>.D
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MA<3>.D
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MA<4>.D 11.0
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MA<5>.D 11.0
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MA<6>.D 10.0
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MA<7>.D 11.0
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MA<8>.D 10.0
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MA<9>.D 10.0
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MA<3>.D 10.0
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MA<4>.D 10.0
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MA<5>.D 11.0
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MA<6>.D 10.0
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MA<7>.D 10.0
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MA<8>.D 10.0
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MA<9>.D 11.0
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MEMW_n.D
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OVL.CE
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RAMCS_n.D 10.0
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RAMCS_n.D
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RAS_n.D
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RW_sync<1>.D
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SDRAM/init_done.CE
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@ -800,43 +801,43 @@ autoconfig_dout<2>.D
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autoconfig_dout<3>.CE
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autoconfig_dout<3>.D
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ctrl_dout<1>.D
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dtack.D 10.0
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dtack.D 10.0
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ide_dtack.D
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mapram_en.D
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ram_dtack.D
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z2_state_FSM_FFd1.D
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z2_state_FSM_FFd2.D 18.7
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z2_state_FSM_FFd2.D 18.7
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--------------------------------------------------------------------------------
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Clock to Setup (tCYC) (nsec)
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(Clock: MEMCLK)
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\ From R R S S S S S S
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\ W W D D D D D D
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\ _ _ R R R R R R
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\ s s A A A A A A
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\ y y M M M M M M
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\ n n / / / / / /
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\ c c i i r r r r
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\ < < n n a a a a
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\ 0 1 i i m m m m
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\ > > t t _ _ _ _
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\ . . _ _ s s s s
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\ Q Q d r t t t t
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\ o e a a a a
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\ n f t t t t
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\ e r e e e e
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\ . e _ _ _ _
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\ Q s F F F F
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\ h S S S S
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\ e M M M M
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\ d _ _ _ _
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\ . F F F F
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\ Q F F F F
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\ d d d d
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\ 1 2 3 4
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\ . . . .
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\ Q Q Q Q
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\ From R R R S S S S S
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\ A W W D D D D D
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\ M _ _ R R R R R
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\ C s s A A A A A
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\ S y y M M M M M
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\ _ n n / / / / /
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\ n c c i i r r r
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\ . < < n n a a a
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\ Q 0 1 i i m m m
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||||
\ > > t t _ _ _
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||||
\ . . _ _ s s s
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\ Q Q d r t t t
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\ o e a a a
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\ n f t t t
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||||
\ e r e e e
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\ . e _ _ _
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\ Q s F F F
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\ h S S S
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||||
\ e M M M
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\ d _ _ _
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||||
\ . F F F
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||||
\ Q F F F
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||||
\ d d d
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\ 1 2 3
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\ . . .
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||||
\ Q Q Q
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||||
\
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||||
\
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\
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@ -844,221 +845,110 @@ z2_state_FSM_FFd2.D 18.7
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AS_n_sync<1>.D
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AS_n_sync<2>.D
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AUTOCONFIG/ac_state<0>.D 10.0
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AUTOCONFIG/ac_state<1>.D 10.0
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AUTOCONFIG/cdtv_configured.CE 10.0
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AUTOCONFIG/ctl_configured.CE 10.0
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AUTOCONFIG/ctrl_base<0>.CE 10.0
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AUTOCONFIG/ctrl_base<1>.CE 10.0
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AUTOCONFIG/ctrl_base<2>.CE 10.0
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AUTOCONFIG/ctrl_base<3>.CE 10.0
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AUTOCONFIG/ide_base<0>.CE 10.0
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AUTOCONFIG/ide_base<1>.CE 10.0
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AUTOCONFIG/ide_base<2>.CE 10.0
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AUTOCONFIG/ide_base<3>.CE 10.0
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AUTOCONFIG/ide_configured.CE 10.0
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AUTOCONFIG/ram_configured.CE 10.0
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BA<0>.CE 10.0 10.0 10.0
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BA<1>.CE 10.0 10.0 10.0
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CAS_n.D 10.0 10.0 10.0 10.0
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CKE.CE 10.0 10.0 10.0
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AUTOCONFIG/ac_state<0>.D 11.0
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AUTOCONFIG/ac_state<1>.D 11.0
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AUTOCONFIG/cdtv_configured.CE 10.0
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AUTOCONFIG/ctl_configured.CE 10.0
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AUTOCONFIG/ctrl_base<0>.CE 10.0
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AUTOCONFIG/ctrl_base<1>.CE 10.0
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AUTOCONFIG/ctrl_base<2>.CE 10.0
|
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AUTOCONFIG/ctrl_base<3>.CE 10.0
|
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AUTOCONFIG/ide_base<0>.CE 10.0
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AUTOCONFIG/ide_base<1>.CE 10.0
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AUTOCONFIG/ide_base<2>.CE 10.0
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AUTOCONFIG/ide_base<3>.CE 10.0
|
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AUTOCONFIG/ide_configured.CE 10.0
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AUTOCONFIG/ram_configured.CE 10.0
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||||
BA<0>.CE 10.0 10.0 10.0
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BA<1>.CE 10.0 10.0 10.0
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CAS_n.D 10.0 10.0 10.0
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CKE.CE 10.0 10.0
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||||
CKE.D
|
||||
ControlReg/dtack.D
|
||||
ControlReg/flash_progbank.D 11.4
|
||||
DQMH.D 10.0 11.0 10.0 11.0
|
||||
DQML.D 10.0 11.0 10.0 11.0
|
||||
ControlReg/flash_progbank.D 11.4
|
||||
DQMH.D 10.0 11.0 10.0
|
||||
DQML.D 11.0 11.0 11.0
|
||||
IDE/ds_delay<0>.D
|
||||
IDE/ds_delay<1>.D
|
||||
IDE/ds_delay<2>.D
|
||||
IDE/ide_enabled.D
|
||||
IOW_n.D
|
||||
LDS_n_sync<1>.D
|
||||
MA<0>.D 11.0 11.0 11.0 10.0
|
||||
MA<10>.D 11.0 11.0 11.0 11.0
|
||||
MA<11>.D 10.0 10.0 10.0 10.0
|
||||
MA<1>.D 11.0 11.0 11.0 10.0
|
||||
MA<2>.D 11.0 11.0 11.0 11.0
|
||||
MA<3>.D 11.0 11.0 11.0 11.0
|
||||
MA<4>.D 11.0 11.0 11.0 11.0
|
||||
MA<5>.D 11.0 11.0 11.0 11.0
|
||||
MA<6>.D 11.0 11.0 11.0 10.0
|
||||
MA<7>.D 11.0 11.0 11.0 11.0
|
||||
MA<8>.D 11.0 11.0 11.0 10.0
|
||||
MA<9>.D 10.0 10.0 10.0 10.0
|
||||
MEMW_n.D 10.0 10.0 10.0 10.0
|
||||
OVL.CE 10.0
|
||||
RAMCS_n.D 10.0 10.0 10.0 10.0
|
||||
RAS_n.D 10.0 10.0 10.0 10.0
|
||||
RW_sync<1>.D 10.0
|
||||
SDRAM/init_done.CE 10.0 10.0 10.0 10.0
|
||||
SDRAM/init_refreshed.CE 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
SDRAM/ram_state_FSM_FFd1.D 11.4 11.4 11.4 10.0 11.4
|
||||
SDRAM/ram_state_FSM_FFd2.D 11.4 11.0 11.4 11.4 11.4 11.4
|
||||
SDRAM/ram_state_FSM_FFd3.D 11.4 10.0 10.0 11.4 11.4 11.4 11.4
|
||||
SDRAM/ram_state_FSM_FFd4.D 11.4 11.0 11.4 11.4 11.4 11.0
|
||||
MA<0>.D 11.0 11.0 11.0
|
||||
MA<10>.D 11.0 11.0 11.0
|
||||
MA<11>.D 10.0 10.0 10.0
|
||||
MA<1>.D 11.0 11.0 11.0
|
||||
MA<2>.D 11.0 11.0 11.0
|
||||
MA<3>.D 11.0 11.0 11.0
|
||||
MA<4>.D 11.0 11.0 11.0
|
||||
MA<5>.D 11.0 11.0 11.0
|
||||
MA<6>.D 11.0 11.0 11.0
|
||||
MA<7>.D 11.0 11.0 11.0
|
||||
MA<8>.D 11.0 11.0 11.0
|
||||
MA<9>.D 11.0 11.0 11.0
|
||||
MEMW_n.D 11.0 11.0 11.0
|
||||
OVL.CE 10.0
|
||||
RAMCS_n.D 11.0 11.0 11.0 11.0
|
||||
RAS_n.D 11.0 11.0 11.0
|
||||
RW_sync<1>.D 10.0
|
||||
SDRAM/init_done.CE 10.0 10.0 10.0
|
||||
SDRAM/init_refreshed.CE 10.0 10.0 10.0 10.0 10.0
|
||||
SDRAM/ram_state_FSM_FFd1.D 11.0 11.4 11.4 10.0
|
||||
SDRAM/ram_state_FSM_FFd2.D 11.4 11.0 11.4 11.4 11.4
|
||||
SDRAM/ram_state_FSM_FFd3.D 11.0 10.0 10.0 11.0 11.0 11.0
|
||||
SDRAM/ram_state_FSM_FFd4.D 11.4 11.0 11.4 11.4 11.4
|
||||
SDRAM/refresh_request<1>.D
|
||||
SDRAM/refreshing.D 10.0 10.0 10.0 10.0
|
||||
SDRAM/timer_tRFC<0>.D 10.0 10.0 10.0 10.0
|
||||
SDRAM/timer_tRFC<1>.D 10.0 10.0 10.0 10.0
|
||||
SDRAM/refreshing.D 10.0 10.0 10.0
|
||||
SDRAM/timer_tRFC<0>.D 10.0 10.0 10.0
|
||||
SDRAM/timer_tRFC<1>.D 10.0 10.0 10.0
|
||||
UDS_n_sync<1>.D
|
||||
autoconf_dtack.D
|
||||
autoconfig_dout<0>.CE 10.0
|
||||
autoconfig_dout<0>.CE 10.0
|
||||
autoconfig_dout<0>.D
|
||||
autoconfig_dout<1>.CE 10.0
|
||||
autoconfig_dout<1>.CE 10.0
|
||||
autoconfig_dout<1>.D
|
||||
autoconfig_dout<2>.CE 10.0
|
||||
autoconfig_dout<2>.CE 10.0
|
||||
autoconfig_dout<2>.D
|
||||
autoconfig_dout<3>.CE 10.0
|
||||
autoconfig_dout<3>.CE 10.0
|
||||
autoconfig_dout<3>.D
|
||||
ctrl_dout<1>.D 12.2
|
||||
dtack.D 11.0
|
||||
ctrl_dout<1>.D 11.4
|
||||
dtack.D 11.0
|
||||
ide_dtack.D
|
||||
mapram_en.D 11.8
|
||||
ram_dtack.D 11.0 11.0 11.0 11.0 11.0
|
||||
mapram_en.D 11.4
|
||||
ram_dtack.D 10.0 10.0 10.0 10.0
|
||||
z2_state_FSM_FFd1.D
|
||||
z2_state_FSM_FFd2.D 20.1
|
||||
z2_state_FSM_FFd2.D 20.1
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: MEMCLK)
|
||||
|
||||
\ From S S S S S U U a
|
||||
\ D D D D D D D u
|
||||
\ R R R R R S S t
|
||||
\ A A A A A _ _ o
|
||||
\ M M M M M n n c
|
||||
\ / / / / / _ _ o
|
||||
\ r r r t t s s n
|
||||
\ e e e i i y y f
|
||||
\ f f f m m n n _
|
||||
\ r r r e e c c d
|
||||
\ e e e r r < < t
|
||||
\ s s s _ _ 0 1 a
|
||||
\ h h h t t > > c
|
||||
\ _ _ i R R . . k
|
||||
\ r r n F F Q Q .
|
||||
\ e e g C C Q
|
||||
\ q q . < <
|
||||
\ u u Q 0 1
|
||||
\ e e > >
|
||||
\ s s . .
|
||||
\ t t Q Q
|
||||
\ < <
|
||||
\ 0 1
|
||||
\ > >
|
||||
\ . .
|
||||
\ Q Q
|
||||
\
|
||||
\
|
||||
\
|
||||
To \------------------------------------------------
|
||||
|
||||
AS_n_sync<1>.D
|
||||
AS_n_sync<2>.D
|
||||
AUTOCONFIG/ac_state<0>.D 10.0
|
||||
AUTOCONFIG/ac_state<1>.D 10.0
|
||||
AUTOCONFIG/cdtv_configured.CE
|
||||
AUTOCONFIG/ctl_configured.CE 10.0
|
||||
AUTOCONFIG/ctrl_base<0>.CE 10.0
|
||||
AUTOCONFIG/ctrl_base<1>.CE 10.0
|
||||
AUTOCONFIG/ctrl_base<2>.CE 10.0
|
||||
AUTOCONFIG/ctrl_base<3>.CE 10.0
|
||||
AUTOCONFIG/ide_base<0>.CE 10.0
|
||||
AUTOCONFIG/ide_base<1>.CE 10.0
|
||||
AUTOCONFIG/ide_base<2>.CE 10.0
|
||||
AUTOCONFIG/ide_base<3>.CE 10.0
|
||||
AUTOCONFIG/ide_configured.CE 10.0
|
||||
AUTOCONFIG/ram_configured.CE 10.0
|
||||
BA<0>.CE
|
||||
BA<1>.CE
|
||||
CAS_n.D
|
||||
CKE.CE
|
||||
CKE.D
|
||||
ControlReg/dtack.D
|
||||
ControlReg/flash_progbank.D
|
||||
DQMH.D 10.0
|
||||
DQML.D
|
||||
IDE/ds_delay<0>.D 10.0
|
||||
IDE/ds_delay<1>.D
|
||||
IDE/ds_delay<2>.D
|
||||
IDE/ide_enabled.D
|
||||
IOW_n.D
|
||||
LDS_n_sync<1>.D
|
||||
MA<0>.D
|
||||
MA<10>.D
|
||||
MA<11>.D
|
||||
MA<1>.D
|
||||
MA<2>.D
|
||||
MA<3>.D
|
||||
MA<4>.D
|
||||
MA<5>.D
|
||||
MA<6>.D
|
||||
MA<7>.D
|
||||
MA<8>.D
|
||||
MA<9>.D
|
||||
MEMW_n.D
|
||||
OVL.CE
|
||||
RAMCS_n.D
|
||||
RAS_n.D
|
||||
RW_sync<1>.D
|
||||
SDRAM/init_done.CE
|
||||
SDRAM/init_refreshed.CE 10.0 10.0
|
||||
SDRAM/ram_state_FSM_FFd1.D 10.0
|
||||
SDRAM/ram_state_FSM_FFd2.D 11.4 11.0 11.0
|
||||
SDRAM/ram_state_FSM_FFd3.D 11.4 10.0 10.0
|
||||
SDRAM/ram_state_FSM_FFd4.D 10.0 11.0 11.0
|
||||
SDRAM/refresh_request<1>.D 10.0
|
||||
SDRAM/refreshing.D 10.0
|
||||
SDRAM/timer_tRFC<0>.D 10.0 10.0
|
||||
SDRAM/timer_tRFC<1>.D 10.0 10.0
|
||||
UDS_n_sync<1>.D 10.0
|
||||
autoconf_dtack.D 10.0
|
||||
autoconfig_dout<0>.CE 10.0
|
||||
autoconfig_dout<0>.D
|
||||
autoconfig_dout<1>.CE 10.0
|
||||
autoconfig_dout<1>.D
|
||||
autoconfig_dout<2>.CE 10.0
|
||||
autoconfig_dout<2>.D
|
||||
autoconfig_dout<3>.CE 10.0
|
||||
autoconfig_dout<3>.D
|
||||
ctrl_dout<1>.D
|
||||
dtack.D 11.8
|
||||
ide_dtack.D
|
||||
mapram_en.D
|
||||
ram_dtack.D
|
||||
z2_state_FSM_FFd1.D 10.0
|
||||
z2_state_FSM_FFd2.D 11.4
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: MEMCLK)
|
||||
|
||||
\ From a a a a c d f i
|
||||
\ u u u u t t l d
|
||||
\ t t t t r a a e
|
||||
\ o o o o l c s _
|
||||
\ c c c c _ k h d
|
||||
\ o o o o d . _ t
|
||||
\ n n n n o Q e a
|
||||
\ f f f f u n c
|
||||
\ i i i i t a k
|
||||
\ g g g g < b .
|
||||
\ _ _ _ _ 1 l Q
|
||||
\ d d d d > e
|
||||
\ o o o o . d
|
||||
\ u u u u Q .
|
||||
\ t t t t Q
|
||||
\ < < < <
|
||||
\ 0 1 2 3
|
||||
\ > > > >
|
||||
\ . . . .
|
||||
\ Q Q Q Q
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\ From S S S S S S U U
|
||||
\ D D D D D D D D
|
||||
\ R R R R R R S S
|
||||
\ A A A A A A _ _
|
||||
\ M M M M M M n n
|
||||
\ / / / / / / _ _
|
||||
\ r r r r t t s s
|
||||
\ a e e e i i y y
|
||||
\ m f f f m m n n
|
||||
\ _ r r r e e c c
|
||||
\ s e e e r r < <
|
||||
\ t s s s _ _ 0 1
|
||||
\ a h h h t t > >
|
||||
\ t _ _ i R R . .
|
||||
\ e r r n F F Q Q
|
||||
\ _ e e g C C
|
||||
\ F q q . < <
|
||||
\ S u u Q 0 1
|
||||
\ M e e > >
|
||||
\ _ s s . .
|
||||
\ F t t Q Q
|
||||
\ F < <
|
||||
\ d 0 1
|
||||
\ 4 > >
|
||||
\ . . .
|
||||
\ Q Q Q
|
||||
\
|
||||
\
|
||||
\
|
||||
@ -1082,6 +972,117 @@ AUTOCONFIG/ide_configured.CE
|
||||
AUTOCONFIG/ram_configured.CE
|
||||
BA<0>.CE
|
||||
BA<1>.CE
|
||||
CAS_n.D 10.0
|
||||
CKE.CE 10.0
|
||||
CKE.D
|
||||
ControlReg/dtack.D
|
||||
ControlReg/flash_progbank.D
|
||||
DQMH.D 11.0 10.0
|
||||
DQML.D 11.0
|
||||
IDE/ds_delay<0>.D 10.0
|
||||
IDE/ds_delay<1>.D
|
||||
IDE/ds_delay<2>.D
|
||||
IDE/ide_enabled.D
|
||||
IOW_n.D
|
||||
LDS_n_sync<1>.D
|
||||
MA<0>.D 10.0
|
||||
MA<10>.D 11.0
|
||||
MA<11>.D 10.0
|
||||
MA<1>.D 11.0
|
||||
MA<2>.D 11.0
|
||||
MA<3>.D 10.0
|
||||
MA<4>.D 10.0
|
||||
MA<5>.D 11.0
|
||||
MA<6>.D 10.0
|
||||
MA<7>.D 10.0
|
||||
MA<8>.D 10.0
|
||||
MA<9>.D 11.0
|
||||
MEMW_n.D 11.0
|
||||
OVL.CE
|
||||
RAMCS_n.D 11.0
|
||||
RAS_n.D 11.0
|
||||
RW_sync<1>.D
|
||||
SDRAM/init_done.CE 10.0
|
||||
SDRAM/init_refreshed.CE 10.0 10.0 10.0
|
||||
SDRAM/ram_state_FSM_FFd1.D 11.4 10.0
|
||||
SDRAM/ram_state_FSM_FFd2.D 11.4 11.4 11.0 11.0
|
||||
SDRAM/ram_state_FSM_FFd3.D 11.0 11.0 10.0 10.0
|
||||
SDRAM/ram_state_FSM_FFd4.D 11.0 10.0 11.0 11.0
|
||||
SDRAM/refresh_request<1>.D 10.0
|
||||
SDRAM/refreshing.D 10.0 10.0
|
||||
SDRAM/timer_tRFC<0>.D 10.0 10.0 10.0
|
||||
SDRAM/timer_tRFC<1>.D 10.0 10.0 10.0
|
||||
UDS_n_sync<1>.D 10.0
|
||||
autoconf_dtack.D
|
||||
autoconfig_dout<0>.CE
|
||||
autoconfig_dout<0>.D
|
||||
autoconfig_dout<1>.CE
|
||||
autoconfig_dout<1>.D
|
||||
autoconfig_dout<2>.CE
|
||||
autoconfig_dout<2>.D
|
||||
autoconfig_dout<3>.CE
|
||||
autoconfig_dout<3>.D
|
||||
ctrl_dout<1>.D
|
||||
dtack.D
|
||||
ide_dtack.D
|
||||
mapram_en.D
|
||||
ram_dtack.D 10.0
|
||||
z2_state_FSM_FFd1.D 10.0
|
||||
z2_state_FSM_FFd2.D
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: MEMCLK)
|
||||
|
||||
\ From a a a a a c d i
|
||||
\ u u u u u t t d
|
||||
\ t t t t t r a e
|
||||
\ o o o o o l c _
|
||||
\ c c c c c _ k d
|
||||
\ o o o o o d . t
|
||||
\ n n n n n o Q a
|
||||
\ f f f f f u c
|
||||
\ _ i i i i t k
|
||||
\ d g g g g < .
|
||||
\ t _ _ _ _ 1 Q
|
||||
\ a d d d d >
|
||||
\ c o o o o .
|
||||
\ k u u u u Q
|
||||
\ . t t t t
|
||||
\ Q < < < <
|
||||
\ 0 1 2 3
|
||||
\ > > > >
|
||||
\ . . . .
|
||||
\ Q Q Q Q
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
To \------------------------------------------------
|
||||
|
||||
AS_n_sync<1>.D
|
||||
AS_n_sync<2>.D
|
||||
AUTOCONFIG/ac_state<0>.D 11.0
|
||||
AUTOCONFIG/ac_state<1>.D 11.0
|
||||
AUTOCONFIG/cdtv_configured.CE
|
||||
AUTOCONFIG/ctl_configured.CE 10.0
|
||||
AUTOCONFIG/ctrl_base<0>.CE 10.0
|
||||
AUTOCONFIG/ctrl_base<1>.CE 10.0
|
||||
AUTOCONFIG/ctrl_base<2>.CE 10.0
|
||||
AUTOCONFIG/ctrl_base<3>.CE 10.0
|
||||
AUTOCONFIG/ide_base<0>.CE 10.0
|
||||
AUTOCONFIG/ide_base<1>.CE 10.0
|
||||
AUTOCONFIG/ide_base<2>.CE 10.0
|
||||
AUTOCONFIG/ide_base<3>.CE 10.0
|
||||
AUTOCONFIG/ide_configured.CE 10.0
|
||||
AUTOCONFIG/ram_configured.CE 10.0
|
||||
BA<0>.CE
|
||||
BA<1>.CE
|
||||
CAS_n.D
|
||||
CKE.CE
|
||||
CKE.D
|
||||
@ -1114,31 +1115,31 @@ RAS_n.D
|
||||
RW_sync<1>.D
|
||||
SDRAM/init_done.CE
|
||||
SDRAM/init_refreshed.CE
|
||||
SDRAM/ram_state_FSM_FFd1.D 11.0
|
||||
SDRAM/ram_state_FSM_FFd2.D 11.0
|
||||
SDRAM/ram_state_FSM_FFd3.D 11.4
|
||||
SDRAM/ram_state_FSM_FFd4.D 11.0
|
||||
SDRAM/ram_state_FSM_FFd1.D 11.0
|
||||
SDRAM/ram_state_FSM_FFd2.D 11.0
|
||||
SDRAM/ram_state_FSM_FFd3.D 11.0
|
||||
SDRAM/ram_state_FSM_FFd4.D 11.0
|
||||
SDRAM/refresh_request<1>.D
|
||||
SDRAM/refreshing.D
|
||||
SDRAM/timer_tRFC<0>.D
|
||||
SDRAM/timer_tRFC<1>.D
|
||||
UDS_n_sync<1>.D
|
||||
autoconf_dtack.D
|
||||
autoconfig_dout<0>.CE
|
||||
autoconfig_dout<0>.D 11.4
|
||||
autoconfig_dout<1>.CE
|
||||
autoconfig_dout<1>.D 11.0
|
||||
autoconfig_dout<2>.CE
|
||||
autoconfig_dout<2>.D 10.0
|
||||
autoconfig_dout<3>.CE
|
||||
autoconfig_dout<3>.D 11.0
|
||||
ctrl_dout<1>.D 11.0
|
||||
dtack.D 10.0 11.8 11.0 11.8
|
||||
autoconf_dtack.D 10.0
|
||||
autoconfig_dout<0>.CE 10.0
|
||||
autoconfig_dout<0>.D 11.4
|
||||
autoconfig_dout<1>.CE 10.0
|
||||
autoconfig_dout<1>.D 11.0
|
||||
autoconfig_dout<2>.CE 10.0
|
||||
autoconfig_dout<2>.D 10.0
|
||||
autoconfig_dout<3>.CE 10.0
|
||||
autoconfig_dout<3>.D 11.0
|
||||
ctrl_dout<1>.D 10.0
|
||||
dtack.D 11.8 10.0 11.8 11.8
|
||||
ide_dtack.D
|
||||
mapram_en.D
|
||||
ram_dtack.D
|
||||
z2_state_FSM_FFd1.D
|
||||
z2_state_FSM_FFd2.D 10.0 20.1 11.4
|
||||
z2_state_FSM_FFd2.D 11.4 10.0 11.4
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
@ -1177,8 +1178,8 @@ z2_state_FSM_FFd2.D 10.0 20.1 11.4
|
||||
|
||||
AS_n_sync<1>.D
|
||||
AS_n_sync<2>.D
|
||||
AUTOCONFIG/ac_state<0>.D 10.0 10.0
|
||||
AUTOCONFIG/ac_state<1>.D 10.0 10.0
|
||||
AUTOCONFIG/ac_state<0>.D 11.0 11.0
|
||||
AUTOCONFIG/ac_state<1>.D 11.0 11.0
|
||||
AUTOCONFIG/cdtv_configured.CE
|
||||
AUTOCONFIG/ctl_configured.CE 10.0 10.0
|
||||
AUTOCONFIG/ctrl_base<0>.CE 10.0 10.0
|
||||
@ -1225,9 +1226,9 @@ RAS_n.D
|
||||
RW_sync<1>.D
|
||||
SDRAM/init_done.CE
|
||||
SDRAM/init_refreshed.CE
|
||||
SDRAM/ram_state_FSM_FFd1.D 11.4 11.0 11.0 11.0
|
||||
SDRAM/ram_state_FSM_FFd1.D 11.0 11.0 11.0 11.0
|
||||
SDRAM/ram_state_FSM_FFd2.D 11.4 11.0 11.0 11.0
|
||||
SDRAM/ram_state_FSM_FFd3.D 11.4 11.4 10.0 11.4
|
||||
SDRAM/ram_state_FSM_FFd3.D 11.0 11.0 10.0 11.0
|
||||
SDRAM/ram_state_FSM_FFd4.D 11.4 11.4 11.0 11.4
|
||||
SDRAM/refresh_request<1>.D
|
||||
SDRAM/refreshing.D
|
||||
@ -1243,11 +1244,11 @@ autoconfig_dout<2>.CE 10.0 10.0
|
||||
autoconfig_dout<2>.D
|
||||
autoconfig_dout<3>.CE 10.0 10.0
|
||||
autoconfig_dout<3>.D
|
||||
ctrl_dout<1>.D 12.2 12.2
|
||||
ctrl_dout<1>.D 11.4 11.4
|
||||
dtack.D 11.0 11.8 11.0 11.0
|
||||
ide_dtack.D
|
||||
mapram_en.D 11.8 11.8 11.8
|
||||
ram_dtack.D 11.0 11.0 11.0
|
||||
mapram_en.D 11.4 11.4 11.4
|
||||
ram_dtack.D 10.0 10.0 10.0
|
||||
z2_state_FSM_FFd1.D 10.0 10.0
|
||||
z2_state_FSM_FFd2.D 20.1 11.4 19.7 11.0 11.4
|
||||
|
||||
|
||||
@ -36,6 +36,7 @@ NET "DQMH" LOC = "P19" ;
|
||||
NET "DQML" LOC = "P17" ;
|
||||
NET "DTACK_n" LOC = "P56" ;
|
||||
NET "ECLK" LOC = "P71" ;
|
||||
NET "EXTEN_n" LOC = "P10" ;
|
||||
NET "FLASH_A18" LOC = "P9" ;
|
||||
NET "FLASH_A19" LOC = "P96" ;
|
||||
NET "FLASH_BANK_SEL" LOC = "P8" ;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user