mirror of
https://github.com/LIV2/A4092-dev.git
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824c17327e
- Rename Z_7M to C7M - Rename MYBBUS to MYBUS_n as it is active low - Don't pass ADDR[] into modules if not needed (intreg still missing) - Fix SBG_n in zorro arbiter
95 lines
3.2 KiB
Verilog
95 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
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//
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// MODULE: buffer_control
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// DESCRIPTION:
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// Buffer control logic based on A4091 GAL U205
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//
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module buffer_control (
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input wire CLK,
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input wire RESET_n,
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// --- Control Signals ---
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input wire READ,
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input wire FCS_n,
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input wire DOE,
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inout wire DTACK_n,
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// --- Master/Slave Cycle Controls ---
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input wire MYBUS_n, // A4091 owns the Zorro bus (active low)
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input wire MASTER_n, // SCSI chip is local master (active low)
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input wire SLAVE_n, // Board is selected as a slave (active low)
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// --- Outputs to Transceivers ---
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output reg DBOE_n,
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output reg ABOEL_n,
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output reg ABOEH_n,
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output reg D2Z_n,
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output reg Z2D_n,
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output reg DBLT
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);
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// --- cycle definitions based on u205.pld ---
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wire master_cycle = ~MYBUS_n && ~MASTER_n;
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wire slave_cycle = MYBUS_n && MASTER_n;
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// Logic from u205.pld, qualified by correct cycle types
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wire dboe_logic = (slave_cycle && !SLAVE_n && !READ && !FCS_n) | // Slave Write
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(slave_cycle && !SLAVE_n && READ && !FCS_n && DOE) | // Slave Read
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(master_cycle && SLAVE_n && !READ && !FCS_n && DOE) | // Master Write
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(master_cycle && SLAVE_n && READ && !FCS_n); // Master Read
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wire d2z_logic = (slave_cycle && READ && !FCS_n && !SLAVE_n) | // Slave Read -> Data to Zorro
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(master_cycle && !READ && !FCS_n && SLAVE_n); // Master Write -> Data to Zorro
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wire z2d_logic = (slave_cycle && !READ && !FCS_n && !SLAVE_n) | // Slave Write -> Zorro to Data
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(master_cycle && READ && !FCS_n && SLAVE_n); // Master Read -> Zorro to Data
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wire dblt_latch = ((slave_cycle && !SLAVE_n) || (master_cycle && SLAVE_n)) &&
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!FCS_n && !DTACK_n && DOE;
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always @(posedge CLK or negedge RESET_n) begin
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if (!RESET_n) begin
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DBOE_n <= 1'b1;
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ABOEL_n <= 1'b1;
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ABOEH_n <= 1'b1;
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D2Z_n <= 1'b1;
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Z2D_n <= 1'b1;
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DBLT <= 1'b0;
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end else begin
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// Buffers are disabled unless a valid master or slave cycle is active
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DBOE_n <= !dboe_logic;
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D2Z_n <= !d2z_logic;
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Z2D_n <= !z2d_logic;
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// Address Buffers
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if (slave_cycle) begin
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ABOEL_n <= 1'b0; // Enabled
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ABOEH_n <= 1'b0; // Enabled
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end else if (master_cycle) begin
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// ABOEH goes high (disabled) after FCS asserts
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if (!FCS_n) begin
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ABOEH_n <= 1'b1;
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end else begin
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ABOEH_n <= 1'b0;
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end
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// ABOEL remains enabled throughout the master cycle
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ABOEL_n <= 1'b0;
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end else begin
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// During arbitration or idle states, address buffers are enabled
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// to allow the host to see the address space.
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ABOEL_n <= 1'b0;
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ABOEH_n <= 1'b0;
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end
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// Data Latch
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if (dblt_latch) begin
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DBLT <= 1'b1;
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end else if (FCS_n) begin
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DBLT <= 1'b0;
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end
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end
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end
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endmodule
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