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https://github.com/LIV2/A4092-dev.git
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146 lines
5.2 KiB
Plaintext
146 lines
5.2 KiB
Plaintext
PARTNO 391581-02 ;
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NAME U205 ;
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DATE April 1, 1993 ;
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REV 5 ;
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DESIGNER Dave Haynie ;
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COMPANY Commodore ;
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ASSEMBLY A4091 ;
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LOCATION West Chester ;
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DEVICE g22v10 ;
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/************************************************************************/
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/* */
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/* A4091 Buffer and termination control. */
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/* */
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/* This device manages data buffer direction, enable, and latch */
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/* functions, address buffer enable, and slave cycle termination. */
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/* */
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/************************************************************************/
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/* */
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/* DEVICE DATA: */
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/* */
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/* Device: 22V10-15 */
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/* Clock: CLK (25MHz) */
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/* Unused: NONE */
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/* */
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/************************************************************************/
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/* */
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/* REVISION HISTORY: */
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/* */
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/* DBH Jul 8: Original version. */
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/* DBH Oct 26: Extended data latching function. */
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/* DBH Nov 2: Modified DTACK again for fast SCSI slave cycle */
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/* termination. */
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/* DBH Nov 19: Changed DBOE for self-reference support. */
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/* DBH Mar 30: Added NOZ3 term for quick Zorro III disconnect, */
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/* to eliminate the multiple A4091 problem. */
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/* DBH Apr 1: Some more NOZ3-related tweaks. */
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/************************************************************************/
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/** INPUTS: **/
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PIN 1 = CLK ; /* 25MHz system clock. */
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PIN 2 = !SLAVE ; /* Board select. */
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PIN 3 = !MYBUS ; /* The A4091 has the bus. */
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PIN 4 = DOE ; /* Data phase on Zorro III. */
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PIN 5 = FCS ; /* Z3 full cycle strobe. */
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PIN 6 = READ ; /* The Zorro III read cycle. */
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PIN 7 = !SLACK ; /* The NCR 53C710 slave acknowledge. */
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PIN 8 = !NOZ3 ; /* Get off the Z3 bus? */
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PIN 9 = INTREG ; /* Interrupt register access. */
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PIN 10 = !INTVEC ; /* Interrupt vector access. */
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PIN 11 = !CFGOUT ; /* Configuration chain output. */
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PIN 13 = !NACK ; /* ROM acknowledge. */
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PIN 14 = !MTCR ; /* Zorro III burst strobe. */
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PIN 15 = !MASTER ; /* SCSI chip owns the A4091 bus. */
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PIN 16 = !SID ; /* SCSI ID. */
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/** OUTPUTS: **/
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PIN 18 = !D2Z ; /* Data is transferred to Zorro III bus. */
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PIN 19 = !Z2D ; /* Data is transferred from Zorro III bus. */
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PIN 20 = DBLT ; /* Data is latched. */
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PIN 21 = !DBOE ; /* Data transfer enable. */
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PIN 22 = !ABOEL ; /* Low order address transfer enable. */
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PIN 23 = !ABOEH ; /* High order address transfer enable. */
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/** BIDIRECTIONALS: **/
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PIN 17 = !DTACK ; /* Zorro III termination. */
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/** LOGICAL TERMS: **/
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/* It takes both MYBUS and MASTER to fully qualify a cycle. If MYBUS is
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asserted but master not, we're in the process of bus arbitration. If
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MASTER is asserted but not MYBUS, the SCSI chip is master of the A4091
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bus and waiting for a grant to the Zorro bus. In both of these cases,
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as little as possible should be done. */
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mastercyc = MYBUS & MASTER;
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slavecyc = !MYBUS & !MASTER;
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/** OUTPUT TERMS: **/
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/* This is the data output enable control. When data buffers are
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pointed toward the board, they can turn on early in the cycle.
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This is a write for slave access, a read for DMA access. When
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the data buffers are pointed out toward the bus, the have to
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wait until DOE to turn on; this is a slave read or DMA write.
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When the board responds to itself, the buffers are left off. If
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the NOZ3 signal is asserted on a write (eg, master driving the
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Zorro III bus), DBOE must be negated immediately. */
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DBOE = slavecyc & SLAVE & !READ & FCS
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# slavecyc & SLAVE & READ & FCS & DOE
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# mastercyc & !SLAVE & !READ & FCS & DOE & !ABOEH & !NOZ3
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# mastercyc & !SLAVE & READ & FCS;
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/* The data buffer direction calculations are very simple. The data to
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Zorro III connection is made for slave reads or DMA writes. The Zorro III
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to data bus connection is made for slave writes or DMA reads. */
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D2Z = slavecyc & READ & FCS & SLAVE
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# mastercyc & !READ & FCS & !SLAVE;
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Z2D = slavecyc & !READ & FCS & SLAVE
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# mastercyc & READ & FCS & !SLAVE;
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/* For either kind of access, data is latched when DTACK is asserted and
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we're in data time. Data is held through the end of the cycle. */
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DBLT = slavecyc & FCS & DTACK & DOE & SLAVE
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# mastercyc & FCS & DTACK & DOE & !SLAVE
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# DBLT & FCS;
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/* The address buffer controls. I want addresses going in unless the SCSI
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device has been granted the A4091 bus. If so, addresses only go out when
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the A4091 has been granted the Zorro III bus. High order addresses also
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go off quickly after FCS is asserted. */
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ABOEL.D = slavecyc
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# mastercyc & !FCS
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# mastercyc & FCS & ABOEL;
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ABOEL.AR = NOZ3;
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ABOEH.D = slavecyc
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# mastercyc & !FCS;
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ABOEH.AR = NOZ3;
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/* The board needs to generate a DTACK here for slave accesses. Most
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of the slave terminations are very simple, since they're either
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based on a termination signal (SLACK for SCSI, NACK for ROM)
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or they're instant (interrupt vector R/W). During configuration,
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any write should also be instantly terminated, that would be a
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configuration register write (reads are governed by ROM access). */
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DTACK = SLAVE & FCS & DOE & SLACK
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# SLAVE & FCS & DOE & INTREG
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# SLAVE & FCS & DOE & INTVEC
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# SLAVE & FCS & DOE & SID
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# SLAVE & FCS & DOE & NACK
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# SLAVE & FCS & DOE & !CFGOUT & !READ
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# SLAVE & FCS & DOE & DTACK;
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DTACK.OE = SLAVE & FCS & !NOZ3;
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