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119 lines
3.7 KiB
Plaintext
119 lines
3.7 KiB
Plaintext
PARTNO 391583-02 ;
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NAME U202 ;
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DATE June 30, 1992 ;
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REV 0 ;
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DESIGNER Dave Haynie ;
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COMPANY Commodore ;
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ASSEMBLY A4091 ;
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LOCATION West Chester ;
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DEVICE g22V10 ;
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/************************************************************************/
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/* */
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/* A4091 AutoConfig */
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/* */
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/* This device manages various aspects of autoconfiguration, along */
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/* with some address decoding and Zorro III signal generation. */
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/* */
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/************************************************************************/
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/* */
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/* DEVICE DATA: */
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/* */
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/* Device: 22V10-15 */
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/* Clock: NONE */
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/* Unused: NONE */
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/* */
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/************************************************************************/
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/* */
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/* REVISION HISTORY: */
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/* */
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/* DBH Jun 20: Original version. */
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/* */
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/************************************************************************/
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/** INPUTS: **/
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PIN 1 = !MATCH ; /* Address comparator match. */
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PIN [2..7] = [A6..1] ; /* Low order address, A1 is really A8 */
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PIN 8 = READ ; /* Z3 read strobe. */
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PIN 9 = !DS3 ; /* Z3 high order data strobe. */
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PIN 10 = FCS ; /* Z3 full cycle strobe. */
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PIN 11 = FC1 ; /* Function codes */
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PIN 13 = FC0 ;
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PIN 14 = !BERR ; /* Bus error */
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PIN 15 = !CFGIN ; /* Configuration chain input */
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PIN 16 = !RST ; /* Z3 reset strobe. */
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PIN 17 = !SHUNT ; /* Z2 configuration shunt. */
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/** OUTPUTS: **/
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PIN 18 = !CFGOUT ; /* Configuration chain output */
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PIN 19 = CFGLT ; /* Configuration address latch */
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PIN 20 = !CINH ; /* Z3 cache inhibit */
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PIN 22 = !SLAVE ; /* Normal slave response to Z3 bus. */
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PIN 23 = !INTSPC ; /* Partially qualified interrupt decode. */
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/** USED INTERNALLY: **/
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PIN 21 = !SHUTUP ; /* Card is Shut up. */
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/** INTERNAL TERMS: **/
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/* Valid processor access space? */
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cpuspace = FC0 & FC1;
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dataspace = !FC1 & FC0;
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/* The low-order addresses. */
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field addr = [A6..A1];
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/** OUTPUT TERMS: **/
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/* The board configuration is really quite simple. If there's a
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write to the configuration register space, the configuration address
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is latched and we pass configuration out. If the system is shunted
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(eg, in a Zorro II backplane), configuration out goes immediately.
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Note that the configuration read registers are actually supplied by
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the first part of the boot ROM. */
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CFGLT = addr:44 & dataspace & FCS & !READ & CFGIN & DS3 & !BERR & !RST & !SHUTUP
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# CFGLT & !RST;
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/* CFGOUT must be activated when board is SHUTUP so the next card in
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the config chain can be addressed. */
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CFGOUT = CFGLT & !RST & !FCS
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# SHUTUP & !RST & !FCS
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# CFGOUT & !RST
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# SHUNT;
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/* A write to the SHUTUP address completely deactivates the board.
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But only while not configured, so CFGLT must block SHUTUP */
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/* SHUTUP must block generation of CFGLT, SLAVE, CINH and INTSPC */
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SHUTUP = addr:4c & dataspace & FCS & !READ & CFGIN & DS3 & !BERR & !RST & !CFGLT
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# SHUTUP & !RST;
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/* The slave signal is drive from here for any normal access. When it isn't
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being driven, it is tri-stated, since the interrupt response logic may
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also drive SLAVE. */
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SLAVE = 'b'1;
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SLAVE.OE = !SHUTUP & CFGIN & MATCH & dataspace & FCS & !RST;
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/* The cache should be inhibited for any access to the board. Actually, it
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doesn't matter if we cache ROM, but there's no reason to since its not
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execute-in-place ROM so no performance is lost making it uncached too. */
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CINH = 'b'1;
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CINH.OE = !SHUTUP & CFGIN & MATCH & dataspace & FCS & !RST;
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/* This signal partially qualifies the decode for interrupt response cycles.
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We want to respond to INT2, of course in CPU space only. The rest of
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the decode takes place in U203, including the real A1. */
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INTSPC = !SHUTUP & CFGIN & CFGOUT & FC0 & FC1 & !RST & !A3 & A2;
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INTSPC.OE = 'b'1;
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