diff --git a/RTL/A4092.ucf b/RTL/A4092.ucf
index 5a0b76d..29c881c 100644
--- a/RTL/A4092.ucf
+++ b/RTL/A4092.ucf
@@ -51,7 +51,7 @@ NET "SIZ<1>"      LOC = "P44";
 # P47 - GND
 NET "MTCR_n"      LOC = "P48";
 NET "SID_n"       LOC = "P49";
-# P50 - NC
+NET "DIP_EXT_TERM" LOC = "P50";
 # P51 - NC
 # P52 - NC
 # P53 - NC
diff --git a/RTL/Makefile b/RTL/Makefile
index 2337195..ab9977e 100644
--- a/RTL/Makefile
+++ b/RTL/Makefile
@@ -10,6 +10,15 @@ CPLDFITFLAGS=-loc on -slew slow -init low -terminate keeper  -unused ground -pow
 
 .PHONY:	all clean timing
 
+# default is DIP switch, not FLASH
+#USE_DIP_SWITCH ?= 1
+# default is FLASH
+USE_DIP_SWITCH ?= 0
+
+ifeq ($(USE_DIP_SWITCH),1)
+  DEFINES += USE_DIP_SWITCH
+endif
+
 all:	$(PROJECT).jed timing
 
 $(PROJECT).prj: *.v
diff --git a/RTL/sid_access.v b/RTL/sid_access.v
index 3625a51..7546efc 100644
--- a/RTL/sid_access.v
+++ b/RTL/sid_access.v
@@ -5,6 +5,11 @@ module sid_access (
     input wire RESET_n,
     input wire [27:0] ADDR,
     input wire READ,
+`ifndef USE_DIP_SWITCH
+    input wire [31:24] DIN,
+    output reg [31:24] DOUT,
+    output wire dip_ext_term,
+`endif
     input wire FCS_n,
     input wire slave_cycle,
     input wire configured,
@@ -18,17 +23,30 @@ module sid_access (
 assign SID_n = !(
     slave_cycle &&
     configured &&
+`ifdef USE_DIP_SWITCH
     READ &&
+`endif
     (ADDR[27:18] == 10'b1000110000)
 );
 
 // SID DTACK logic: one-cycle delay when selected
 reg [1:0] sid_state;
 
+`ifndef USE_DIP_SWITCH
+// One-byte DIP shadow register
+reg [7:0] dip_shadow;
+
+assign dip_ext_term = dip_shadow[0];
+`endif
+
 always @(posedge CLK or negedge RESET_n) begin
     if (!RESET_n) begin
         sid_state <= 2'd0;
         sid_dtack <= 0;
+`ifndef USE_DIP_SWITCH
+	DOUT <= 8'hFF;
+	dip_shadow <= 8'h00;
+`endif
     end else begin
         case (sid_state)
             2'd0: begin
@@ -38,9 +56,26 @@ always @(posedge CLK or negedge RESET_n) begin
             end
             2'd1: begin
                 sid_dtack <= 1;
+`ifdef USE_DIP_SWITCH
                 if (FCS_n)
                     sid_state <= 2'd0;
+`else
+		sid_state <= 2'd2;
+
+                if (READ)
+                    DOUT <= dip_shadow;
+                else
+                    dip_shadow <= DIN;
+`endif
             end
+`ifndef USE_DIP_SWITCH
+	    2'd2: begin
+                if (FCS_n) begin
+                    sid_dtack <= 0;
+                    sid_state <= 0;
+                end
+            end
+`endif
         endcase
     end
 end
diff --git a/RTL/top.v b/RTL/top.v
index 289bb10..e9e7676 100644
--- a/RTL/top.v
+++ b/RTL/top.v
@@ -15,6 +15,7 @@ module A4092(
     input READ,
     input [1:0] SIZ,
     output SID_n,
+    output DIP_EXT_TERM,
     inout [31:0] D, // Only [8:0] and [31:24] are used
     output reg CLK,
     output BMASTER,
@@ -270,11 +271,20 @@ rom_access ROM_ACCESS (
   .ROM_WE_n(ROM_WE_n)
 );
 
+`ifndef USE_DIP_SWITCH
+wire [7:0] dip_shadow;
+`endif
+
 sid_access SID_ACCESS (
   .CLK(CLK),
   .RESET_n(IORST_n),
   .ADDR({ADDR, A[7:0]}),
   .READ(READ),
+`ifndef USE_DIP_SWITCH
+  .DIN(D[31:24]),
+  .DOUT(dip_shadow),
+  .dip_ext_term(DIP_EXT_TERM),
+`endif
   .FCS_n(FCS_n_sync[1]),
   .slave_cycle(slave_cycle),
   .configured(configured),
@@ -286,9 +296,12 @@ assign MTCR_n  = MTCR_n_int;
 assign CBACK_n = CBACK_n_int;
 assign STERM_n = STERM_n_int;
 
-assign D[31:28] = (autoconfig_cycle) ? autoconfig_dout :
+assign D[31:24] = (autoconfig_cycle) ? autoconfig_dout :
                   (int_dtack)        ? intreg_dout     :
-                  4'hF;
+`ifndef USE_DIP_SWITCH
+                  (sid_dtack) ? dip_shadow :
+`endif
+                  8'hFF;
 
 assign DBOE_n  = DBOE_n_int;
 assign ABOEL_n = ABOEL_n_int;