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RTL: Fix signal naming and hook up right bits of DIP

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This commit is contained in:
Stefan Reinauer 2025-06-07 11:29:29 -07:00
parent 67f86c9a51
commit 758385b5f3
3 changed files with 11 additions and 12 deletions
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4
RTL/A4092.ucf
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@ -105,8 +105,8 @@ NET "MASTER_n" LOC = "P100";
NET "SLACK_n" LOC = "P101";
NET "D<13>" LOC = "P102";
NET "SINT_n" LOC = "P103";
NET "SCSI_SREG" LOC = "P104";
NET "STERM_n" LOC = "P105";
NET "SCSI_SREG_n" LOC = "P104";
NET "SCSI_STERM_n" LOC = "P105";
NET "INT2_n" LOC = "P106";
NET "D<12>" LOC = "P107";
# P108 - GND

4
RTL/sid_access.v
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@ -6,8 +6,8 @@ module sid_access (
input wire [23:17] ADDR,
input wire READ,
`ifndef USE_DIP_SWITCH
input wire [31:24] DIN,
output reg [31:24] DOUT,
input wire [7:0] DIN,
output reg [7:0] DOUT,
output wire dip_ext_term,
`endif
input wire FCS_n,

15
RTL/top.v
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@ -72,15 +72,14 @@ module A4092(
// Board Control
output wire SID_n,
output wire DIP_EXT_TERM
output wire DIP_EXT_TERM,
// Unused:
// We _never_ issue a CBACK, since BURST isn't supported
// input CBREQ_n,
// output CBACK_n,
// output MTACK_n,
//
// input Z_FCS,
input CBREQ_n,
output CBACK_n,
output MTACK_n,
input Z_FCS
);
@ -119,7 +118,7 @@ wire D2Z_n_int;
wire Z2D_n_int;
wire DBLT_int;
`ifndef USE_DIP_SWITCH
wire dip_shadow;
wire [7:0] dip_shadow;
`endif
wire slave_cycle = !MASTER_n && !BMASTER;
@ -319,7 +318,7 @@ sid_access SID_ACCESS (
.ADDR(full_addr[23:17]),
.READ(READ),
`ifndef USE_DIP_SWITCH
.DIN(D[31:24]),
.DIN(D[7:0]),
.DOUT(dip_shadow),
.dip_ext_term(DIP_EXT_TERM),
`endif